DP83867IR, DP83867CR
ZHCSDE3G –FEBRUARY 2015 –REVISED OCTOBER 2022
www.ti.com.cn
表6-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
HTQFP
VQFN
RGMII
MAC INTERFACES
MII TRANSMIT CLOCK: TX_CLK is a continuous clock signal driven by the
PHY during 10 Mbps or 100 Mbps MII mode. TX_CLK clocks the data or error
out of the MAC layer and into the PHY.
TX_CLK
30
O
The TX_CLK clock frequency is 2.5 MHz in 10BASE-Te and 25 MHz in
100BASE-TX mode.
GMII TRANSMIT DATA Bit 7: This signal carries data from the MAC to the
PHY in GMII mode. It is synchronous to the transmit clock GTX_CLK.
TX_D7
TX_D6
TX_D5
TX_D4
31
30
33
34
I, PD
I, PD
I, PD
I, PD
GMII TRANSMIT DATA Bit 6: This signal carries data from the MAC to the
PHY in GMII mode. It is synchronous to the transmit clock GTX_CLK.
GMII TRANSMIT DATA Bit 5: This signal carries data from the MAC to the
PHY in GMII mode. It is synchronous to the transmit clock GTX_CLK.
GMII TRANSMIT DATA Bit 4: This signal carries data from the MAC to the
PHY in GMII mode. It is synchronous to the transmit clock GTX_CLK.
TRANSMIT DATA Bit 3: This signal carries data from the MAC to the PHY in
GMII, RGMII, and MII modes. In GMII and RGMII modes, it is synchronous to
the transmit clock GTX_CLK. In MII mode, it is synchronous to the transmit
clock TX_CLK.
TX_D3
TX_D2
TX_D1
TX_D0
35
36
37
38
25
26
27
28
I, PD
I, PD
I, PD
I, PD
TRANSMIT DATA Bit 2: This signal carries data from the MAC to the PHY in
GMII, RGMII, and MII modes. In GMII and RGMII modes, it is synchronous to
the transmit clock GTX_CLK. In MII mode, it is synchronous to the transmit
clock TX_CLK.
TRANSMIT DATA Bit 1: This signal carries data from the MAC to the PHY in
GMII, RGMII, and MII modes. In GMII and RGMII modes, it is synchronous to
the transmit clock GTX_CLK. In MII mode, it is synchronous to the transmit
clock TX_CLK.
TRANSMIT DATA Bit 0: This signal carries data from the MAC to the PHY in
GMII, RGMII, and MII modes. In GMII and RGMII modes, it is synchronous to
the transmit clock GTX_CLK. In MII mode, it is synchronous to the transmit
clock TX_CLK.
GMII TRANSMIT ERROR: This signal is used in GMII mode to force the PHY
to transmit invalid symbols. The TX_ER signal is synchronous to the GMII
transmit clock GTX_CLK.
In MII 4B nibble mode, assertion of Transmit Error by the controller causes
the PHY to issue invalid symbols followed by Halt (H) symbols until
deassertion occurs.
TX_ER
39
I, PD
In GMII mode, assertion causes the PHY to emit one or more code-groups
that are invalid data or delimiter in the transmitted frame.
GMII and RGMII TRANSMIT CLOCK: This continuous clock signal is sourced
from the MAC layer to the PHY. Nominal frequency is 125 MHz.
GTX_CLK
RX_CLK
40
43
29
32
I, PD
O
RECEIVE CLOCK: Provides the recovered receive clocks for different modes
of operation:
2.5 MHz in 10-Mbps mode.
25 MHz in 100-Mbps mode.
125 MHz in 1000-Mbps GMII and RGMII mode.
RECIEVE DATA Bit 0: This signal carries data from the PHY to the MAC in
GMII, RGMII, and MII modes. It is synchronous to the receive clock RX_CLK.
RX_D0
RX_D1
RX_D2
RX_D3
44
45
46
47
33
34
35
36
S, O, PD
O, PD
RECIEVE DATA Bit 1: This signal carries data from the PHY to the MAC in
GMII, RGMII, and MII modes. It is synchronous to the receive clock RX_CLK.
RECIEVE DATA Bit 2: This signal carries data from the PHY to the MAC in
GMII, RGMII, and MII modes. It is synchronous to the receive clock RX_CLK.
S, O, PD
O, PD
RECIEVE DATA Bit 3: This signal carries data from the PHY to the MAC in
GMII, RGMII, and MII modes. It is synchronous to the receive clock RX_CLK.
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