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DP83848IVVX/NOPB PDF预览

DP83848IVVX/NOPB

更新时间: 2024-02-05 13:17:21
品牌 Logo 应用领域
德州仪器 - TI 以太网局域网(LAN)标准以太网:16GBASE-T电信电信集成电路电信电路网络接口
页数 文件大小 规格书
86页 788K
描述
支持 SNI 和 JTAG 接口、具有工业级温度范围的 10/100Mbps 以太网 PHY 收发器 | PT | 48 | -40 to 85

DP83848IVVX/NOPB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QFP, QFP48,.35SQ,20Reach Compliance Code:not_compliant
风险等级:5.44数据速率:100000 Mbps
JESD-30 代码:S-PQFP-G48端子数量:48
收发器数量:1最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP48,.35SQ,20
封装形状:SQUARE封装形式:FLATPACK
电源:3.3 V认证状态:Not Qualified
子类别:Network Interfaces标称供电电压:3.3 V
表面贴装:YES技术:CMOS
电信集成电路类型:ETHERNET TRANSCEIVER温度等级:AUTOMOTIVE
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUADBase Number Matches:1

DP83848IVVX/NOPB 数据手册

 浏览型号DP83848IVVX/NOPB的Datasheet PDF文件第7页浏览型号DP83848IVVX/NOPB的Datasheet PDF文件第8页浏览型号DP83848IVVX/NOPB的Datasheet PDF文件第9页浏览型号DP83848IVVX/NOPB的Datasheet PDF文件第11页浏览型号DP83848IVVX/NOPB的Datasheet PDF文件第12页浏览型号DP83848IVVX/NOPB的Datasheet PDF文件第13页 
1.0 Pin Descriptions  
The DP83848I pins are classified into the following inter- Note: Strapping pin option. Please see Section 1.7 for strap  
face categories (each interface is described in the sections  
that follow):  
definitions.  
All DP83848I signal pins are I/O cells regardless of the par-  
ticular use. The definitions below define the functionality of  
the I/O cells for each pin.  
— Serial Management Interface  
— MAC Data Interface  
— Clock Interface  
Type: I  
Input  
— LED Interface  
Type: O  
Type: I/O  
Type OD  
Output  
— JTAG Interface  
Input/Output  
Open Drain  
— Reset and Power Down  
— Strap Options  
Type: PD,PU Internal Pulldown/Pullup  
Type: S Strapping Pin (All strap pins have weak in-  
— 10/100 Mb/s PMD Interface  
— Special Connect Pins  
— Power and Ground pins  
ternal pull-ups or pull-downs. If the default  
strap value is needed to be changed then an  
external 2.2 kresistor should be used.  
Please see Section 1.7 for details.)  
1.1 Serial Management Interface  
Signal Name  
Type  
Pin #  
Description  
MDC  
I
31  
MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO  
management data input/output serial interface which may be  
asynchronous to transmit and receive clocks. The maximum clock  
rate is 25 MHz with no minimum clock rate.  
MDIO  
I/O  
30  
MANAGEMENT DATA I/O: Bi-directional management instruc-  
tion/data signal that may be sourced by the station management  
entity or the PHY. This pin requires a 1.5 kpullup resistor.  
1.2 MAC Data Interface  
Signal Name  
Type  
Pin #  
Description  
TX_CLK  
O
1
MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100  
Mb/s mode or 2.5 MHz in 10 Mb/s mode derived from the 25 MHz  
reference clock.  
Unused in RMII mode. The device uses the X1 reference clock in-  
put as the 50 MHz reference for both transmit and receive.  
SNI TRANSMIT CLOCK: 10 MHz Transmit clock output in 10 Mb  
SNI mode. The MAC should source TX_EN and TXD_0 using this  
clock.  
TX_EN  
I, PD  
2
MII TRANSMIT ENABLE: Active high input indicates the pres-  
ence of valid data inputs on TXD[3:0].  
RMII TRANSMIT ENABLE: Active high input indicates the pres-  
ence of valid data on TXD[1:0].  
SNI TRANSMIT ENABLE: Active high input indicates the pres-  
ence of valid data on TXD_0.  
TXD_0  
TXD_1  
TXD_2  
TXD_3  
I
3
4
5
6
MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0],  
that accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s  
mode or 25 MHz in 100 Mb/s mode).  
RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0],  
that accept data synchronous to the 50 MHz reference clock.  
S, I, PD  
SNI TRANSMIT DATA: Transmit data SNI input pin, TXD_0, that  
accept data synchronous to the TX_CLK (10 MHz in 10 Mb/s SNI  
mode).  
9
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DP83848IVVX/NOPB 替代型号

型号 品牌 替代类型 描述 数据表
DP83848IVV/NOPB TI

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支持 SNI 和 JTAG 接口、具有工业级温度范围的 10/100Mbps 以太网 PH

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