Datasheet > DP83820

DP83820

更新时间： 2024-01-23 00:44:08

品牌	Logo	应用领域
美国国家半导体 - NSC		网络接口控制器 PC 以太网局域网（LAN）标准
页数	文件大小	规格书
87页	1230K
描述
10/100/1000 Mb/s PCI Ethernet Network Interface Controller

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技术参数
数据手册

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DP83820 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	FQFP,	针数：	208
Reach Compliance Code：	unknown	HTS代码：	8542.31.00.01
风险等级：	5.82	Is Samacsys：	N
地址总线宽度：	32	边界扫描：	YES
总线兼容性：	PCI	最大时钟频率：	25 MHz
最大数据传输速率：	125 MBps	外部数据总线宽度：	32
JESD-30 代码：	S-PQFP-G208	长度：	28 mm
低功率模式：	YES	串行 I/O 数：	8
端子数量：	208	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	FQFP	封装形状：	SQUARE
封装形式：	FLATPACK, FINE PITCH	认证状态：	Not Qualified
座面最大高度：	4.1 mm	最大供电电压：	1.95 V
最小供电电压：	1.65 V	标称供电电压：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	28 mm	uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches：	1

DP83820 数据手册

2.0 Pin Descriptions ^(Continued)

PCI Interface

Symbol

SERRN

Pin No(s)

Direction

Description

I/O

System Error: This signal is asserted low by DP83820 during address parity

errors and system errors if enabled.

STOPN

TRDYN

I/O

Stop: This signal is asserted low by the target device to request the master

device to stop the current transaction.

Target Ready: As a target, this signal will be asserted low when the (slave)

device is ready to complete the current data phase transaction. This signal is

used in conjunction with the IRDYN signal. Data transaction takes place at the

rising edge of PCICLK when both IRDYN and TRDYN are asserted low. As a

master, this signal indicates that the target is ready for the data during write

operation and with the data during read operation.

PMEN

3VAUX

175

Power Management Event: This signal is asserted low by DP83820 to indicate

that a power management event has occurred.

PCI Aux Voltage Sense: This pin is used to sense the presence of a 3.3v

auxiliary supply in order to define the PME Support available.

This pin pad has an internal weak pull down.

PWRGOOD

PCI bus power good: Connected to PCI bus 3.3v power, this pin is used to

sense the presence of PCI bus power during the D3 power management state.

This pin pad has an internal weak pull down.

CLKRUNN

AD63-32

I/O

Clockrun: This signal is asserted low by DP83820 to indicate that a Clockrun

Event has occurred.

44, 45, 47, 48,

49, 50, 52, 53,

54, 55, 57, 58,

59, 61, 62, 63,

64, 65, 67, 68,

69, 70, 72, 73,

74, 75, 77, 78,

79, 81, 82, 83

64-bit Extension Address and Data: Multiplexed address and data bus.

Provides upper address bits during 64-bit DAC command. During data phase,

used for transferring upper 32-bits of a 64-bit data transaction.

CBEN7-4

38, 39, 41, 42

I/O

64-bit Extension Bus Command/Byte Enables: During the address phase

these signals define the “bus command” for a 64-bit DAC command. During a

64-bit data phase these pins indicate which byte lanes contain valid data.

CBEN4 applies to byte 4(bits 39-32) and CBEN7 applies to byte 7(bits 63-56).

REQ64N

ACK64N

I/O

Request 64-bit Transfer: The DP83820 will assert this signal low to request a

64-bit transfer of data. This pin is sampled by the DP83820 during reset to

determine if the device is connected to a 64-bit datapath.

Acknowledge 64-bit Transfer: The DP83820 will samples this signal on bus

master cycles when it has requested a 64-bit data transfer. If both REQ64N and

ACK64N are asserted, then a 64-bit transfer will be performed. As a target, the

DP83820 only supports 32-bit transfers, so it will never assert ACK64N.

PAR64

I/O

Parity Upper DWORD: This signal indicates even parity across AD63-32 and

CBEN7-4 including the PAR64 pin. As a master, PAR64 is driven during

address and write data phases. As a target, the DP83820 only supports 32-bit

transfers, so it will not drive PAR64.

PCIVIO

PCI Bus VIO: This pin should be connected to the VIO pins of the PCI bus. It

provides a direct connection to the ESDPLUS ring for biasing. It may be

connected to 5V if available. It should not be connected to 3.3V unless all

signaling is 3.3V as this will interfere with 5V tolerance. Care should be taken in

connecting this to power supplies when power management functions are

enabled.

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