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DP83820

更新时间： 2024-01-12 09:43:39
品牌 Logo 应用领域
美国国家半导体 - NSC 网络接口控制器PC以太网局域网（LAN）标准
页数 文件大小 规格书
87页 1230K
描述
10/100/1000 Mb/s PCI Ethernet Network Interface Controller

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DP83820 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：FQFP,针数：208
Reach Compliance Code：unknownHTS代码：8542.31.00.01
风险等级：5.82Is Samacsys：N
地址总线宽度：32边界扫描：YES
总线兼容性：PCI最大时钟频率：25 MHz
最大数据传输速率：125 MBps外部数据总线宽度：32
JESD-30 代码：S-PQFP-G208长度：28 mm
低功率模式：YES串行 I/O 数：8
端子数量：208最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：FQFP封装形状：SQUARE
封装形式：FLATPACK, FINE PITCH认证状态：Not Qualified
座面最大高度：4.1 mm最大供电电压：1.95 V
最小供电电压：1.65 V标称供电电压：1.8 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
宽度：28 mmuPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches：1

DP83820 数据手册

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2.0 Pin Descriptions (Continued)  
BIOS ROM/Flash Interface  
Symbol  
MWRN  
Pin No(s)  
Direction  
Description  
94  
O
BIOS ROM/Flash Write: During a BIOS ROM/Flash access, this signal is  
used to enable data to be written to the Flash device.  
MRDN  
93  
O
BIOS ROM/Flash Read: During a BIOS ROM/Flash access, this signal is  
used to enable data to be read from the Flash device.  
Note: DP83820 supports NM27LV010 for the ROM interface device.  
Clock Interface  
Symbol  
Pin No(s)  
Direction  
Description  
X1  
X2  
122  
I
Crystal/Oscillator Input: This pin is the primary clock reference input for the  
DP83820 IC and must be connected to a 25MHz 0.005% (50ppm) clock source.  
The DP83820 device supports either an external crystal resonator connected  
across pins X1 and X2, or an external CMOS-level oscillator source connected  
to pin X1 only.  
121  
O
Crystal Output: This pin is used in conjunction with the X1 pin to connect to an  
external 25MHz crystal resonator device. This pin must be left unconnected if  
an external CMOS oscillator clock source is utilized. For more information see  
the definition for pin X1.  
Phy And General Purpose Interface  
Symbol  
GP1DUP  
Pin No(s)  
Direction  
Description  
131  
I/O  
General Purpose Pin 1 or Duplex Status: By default, this pin can be used to  
input the Full Duplex status from an external Phy. The pin can also be  
programmed as a general purpose I/O. This pin pad has an internal weak pull  
up.  
GP2  
127  
128  
129  
130  
132  
133  
I/O  
I/O  
I/O  
I/O  
I
General Purpose Pin 2: This pin is a general purpose I/O pin that can be  
programmed as an input or output. This pin has an internal weak pull up.  
GP3  
General Purpose Pin 3: This pin is a general purpose I/O pin that can be  
programmed as an input or output. This pin has an internal weak pull up.  
GP4  
General Purpose Pin 4: This pin is a general purpose I/O pin that can be  
programmed as an input or output. This pin has an internal weak pull up.  
GP5  
General Purpose Pin 5: This pin is a general purpose I/O pin that can be  
programmed as an input or output. This pin has an internal weak pull up.  
PHYLNK  
SPD100  
Phy Link Status: This can be used to input the Phy Link Status. This allows the  
value to be read back from the MAC register space.  
I
100 Mb/s Speed Status: This can be used to input the 100 Mb/s Speed Status  
from an external phy. This is used along with the SPD1000 bit to determine  
current speed status of the Phy.  
SPD1000  
134  
172  
I
1000 Mb/s Speed Status: This can be used to input the 1000 Mb/s Speed  
Status from an external phy. This is used along with the SPD100 bit to  
determine current speed status of the Phy.  
PHYRSTN  
O
Phy Reset: This pin can be used to reset an External Phy.  
7
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