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DP83820 PDF预览

DP83820

更新时间： 2024-01-22 19:41:17
品牌 Logo 应用领域
美国国家半导体 - NSC 网络接口控制器PC以太网局域网（LAN）标准
页数 文件大小 规格书
87页 1230K
描述
10/100/1000 Mb/s PCI Ethernet Network Interface Controller

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DP83820 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：FQFP,针数：208
Reach Compliance Code：unknownHTS代码：8542.31.00.01
风险等级：5.82Is Samacsys：N
地址总线宽度：32边界扫描：YES
总线兼容性：PCI最大时钟频率：25 MHz
最大数据传输速率：125 MBps外部数据总线宽度：32
JESD-30 代码：S-PQFP-G208长度：28 mm
低功率模式：YES串行 I/O 数：8
端子数量：208最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：FQFP封装形状：SQUARE
封装形式：FLATPACK, FINE PITCH认证状态：Not Qualified
座面最大高度：4.1 mm最大供电电压：1.95 V
最小供电电压：1.65 V标称供电电压：1.8 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
宽度：28 mmuPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches：1

DP83820 数据手册

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2.0 Pin Descriptions (Continued)  
Media Independent Interface (MII) - and Gigabit Media Independent Interface (GMII).  
Symbol  
Pin No(s)  
Direction  
Description  
TXD7/MA15,  
TXD6/MA14,  
TXD5/MA13,  
TXD4/MA12,  
TXD3/MA11,  
TXD2/MA10,  
TXD1/MA9,  
TXD0/MA8  
152,  
151,  
148,  
147,  
146,  
145,  
142,  
141  
O
Gigabit Transmit Data: This is a group of 8 signals which are driven  
synchronous to GTXCLK. TXD7 is the most significant bit.  
Transmit Data: This is a group of 4 data signals which are driven synchronous  
to the TXCLK for transmission to the external PMD. TXD3 is the most significant  
bit and TXD0 is the least significant bit. TXD7 through TXD4 are not used in this  
mode  
TBI Transmit Data: In TBI mode, this is the lower 8 bits of the 10-bit TBI  
Transmit data.  
BIOS ROM Address: During external BIOS ROM access, these signals  
become part of the ROM address.  
TXEN/TXD8  
TXER/TXD9  
153  
154  
O
O
Transmit Enable: This signal is synchronous to TXCLK and provides precise  
framing for data carried on TXD3-0 for the external PMD. It is asserted when  
TXD3-0 contains valid data to be transmitted.  
TBI Transmit Data: In TBI mode, this is TXD8 of the 10-bit TBI Transmit data.  
Transmit Error: This signal is synchronous to TXCLK and provides error  
indications and also is used for 1000 Mb/s half-duplex carrier extension and  
packet bursting functions. The DP83820 will only assert this signal in 1000 Mb/s  
mode of operation.  
TBI Transmit Data: In TBI mode, this is TXD9 of the 10-bit TBI Transmit data.  
GTXCLK/  
TXPMACLK  
140  
137  
O
GMII transmit Clock: A continuous clock used for 1000 Mb/s. It is output to an  
external PMD and is the reference clock for Transmit GMII signaling. The clock  
frequency is 125 MHz.  
TBI Transmit Clock: In TBI mode, this is the 125MHz transmit clock to an  
external PMD and is the reference for Transmit TBI signaling.  
REF125  
I
125 MHz Reference Clock: May be optionally connected to a 125 MHz  
oscillator for 1000 Mb/s mode. If not used should be tied high.  
BIOS ROM/Flash Interface  
Symbol  
MCSN  
Pin No(s)  
Direction  
Description  
92  
O
BIOS PROM/Flash Chip Select: During a BIOS ROM/Flash access, this  
signal is used to select the ROM device.  
MD7, MD6,  
MD5, MD4/EEDO,  
MD3, MD2,  
MD1/CFGDISN,  
MD0/PMGDISN  
104, 103,  
102, 101,  
98, 97,  
96,  
I/O  
BIOS ROM/Flash Data Bus: During a BIOS ROM/Flash access these  
signals are used to transfer data to or from the ROM/Flash device.  
MD5:0 and MD7 pin pads have an internal weak pull up.  
MD6 pin pad has an internal weak pull down.  
95,  
MA15/TXD7,  
MA14/TXD6,  
MA13/TXD5,  
MA12/TXD4,  
MA11/TXD3,  
MA10/TXD2,  
MA9/TXD1,  
152,  
151,  
148,  
147,  
146,  
O
BIOS ROM/Flash Address: During a BIOS ROM/Flash access, these  
signals are used to drive the ROM/Flash address.  
145,  
142,  
MA8/TXD0,  
141,  
MA7, MA6,  
114, 113,  
112, 109,  
108, 107,  
106, 105  
MA5, MA4/EECLK,  
MA3/EEDI, MA2,  
MA1, MA0  
6
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