Datasheet > DP83820

DP83820

更新时间： 2024-02-21 05:49:14

品牌	Logo	应用领域
美国国家半导体 - NSC		网络接口控制器 PC 以太网局域网（LAN）标准
页数	文件大小	规格书
87页	1230K
描述
10/100/1000 Mb/s PCI Ethernet Network Interface Controller

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DP83820 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	FQFP,	针数：	208
Reach Compliance Code：	unknown	HTS代码：	8542.31.00.01
风险等级：	5.82	Is Samacsys：	N
地址总线宽度：	32	边界扫描：	YES
总线兼容性：	PCI	最大时钟频率：	25 MHz
最大数据传输速率：	125 MBps	外部数据总线宽度：	32
JESD-30 代码：	S-PQFP-G208	长度：	28 mm
低功率模式：	YES	串行 I/O 数：	8
端子数量：	208	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	FQFP	封装形状：	SQUARE
封装形式：	FLATPACK, FINE PITCH	认证状态：	Not Qualified
座面最大高度：	4.1 mm	最大供电电压：	1.95 V
最小供电电压：	1.65 V	标称供电电压：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	28 mm	uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches：	1

DP83820 数据手册

2.0 Pin Descriptions

PCI Interface

Symbol

AD31-0

Pin No(s)

Direction

Description

188, 189, 190,

191, 192, 193,

194, 195, 199,

200, 202, 203,

204, 207, 208,

1, 14, 15, 17,

18, 19, 21, 22,

23, 25, 26, 28,

29, 31, 32, 33,

I/O

Address and Data: Multiplexed address and data bus. As a bus master, the

DP83820 will drive address during the first bus phase. During subsequent

phases, the DP83820 will either read or write data expecting the target to

increment its address pointer. As a bus target, the DP83820 will decode each

address on the bus and respond if it is the target being addressed.

CBEN3-0

197, 2, 13, 24

I/O

Bus Command/Byte Enable: During the address phase these signals define

the “bus command” or the type of bus transaction that will take place. During the

data phase these pins indicate which byte lanes contain valid data. CBEN0

applies to byte 0 (bits 7-0) and CBEN3 applies to byte 3(bits 31-24).

PCICLK

176

Clock: This PCI Bus clock provides timing for all bus phases. The rising edge

defines the start of each phase. The clock frequency ranges from 0 to 66 MHz.

DEVSELN

I/O

Device Select: As a target, the DP83820 asserts this signal low when it

recognizes its address after FRAMEN is asserted. As a bus master, the

DP83820 samples this signal to insure that the destination address for the data

transfer is recognized by a PCI target.

FRAMEN

GNTN

I/O

Frame: As a bus master, this signal is asserted low to indicate the beginning

and duration of a bus transaction. Data transfer takes place when this signal is

asserted. It is de-asserted before the transaction is in its final phase. As a

target, the device monitors this signal before decoding the address to check if

the current transaction is addressed to it.

185

Grant: This signal is asserted low to indicate to the DP83820 that it has been

granted ownership of the bus by the central arbiter. This input is used when the

DP83820 is acting as a bus master.

IDSEL

INTAN

198

183

Initialization Device Select: This pin is sampled by the DP83820 to identify

when configuration read and write accesses are intended for it.

Interrupt A: This signal is asserted low when an interrupt condition as defined

in the Interrupt Status Register, Interrupt Mask, and Interrupt Enable registers

occurs.

IRDYN

I/O

Initiator Ready: As a bus master, this signal will be asserted low when the

DP83820 is ready to complete the current data phase transaction. This signal is

used in conjunction with the TRYDN signal. Data transaction takes place at the

rising edge of PCICLK when both IRDYN and TRDYN are asserted low. As a

target, this signal indicates that the master has put the data on the bus.

PAR

I/O

Parity: This signal indicates even parity across AD31-0 and CBEN3-0 including

the PAR pin. As a master, PAR is asserted during address and write data

phases. As a target, PAR is asserted during read data phases.

PERRN

Parity Error: The DP83820 as a master or target will assert this signal low to

indicate a parity error on any incoming data (except for special cycles). As a bus

master, it will monitor this signal on all write operations (except for special

cycles).

REQN

RSTN

186

184

Request: The DP83820 will assert this signal low to request the ownership of

the bus to the central arbiter.

Reset: When this signal is asserted all outputs of DP83820 will be tri-stated

and the device will be put into a known state.

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