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DP83816AVNG-EX PDF预览

DP83816AVNG-EX

更新时间： 2024-01-26 00:06:40
品牌 Logo 应用领域
美国国家半导体 - NSC 时钟局域网数据传输PC外围集成电路
页数 文件大小 规格书
106页 800K
描述
IC 4 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144, LQFP-144, Serial IO/Communication Controller

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DP83816AVNG-EX 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LFQFP,针数：144
Reach Compliance Code：compliantHTS代码：8542.31.00.01
风险等级：5.77地址总线宽度：32
边界扫描：NO总线兼容性：PCI
最大时钟频率：25 MHz数据编码/解码方法：NRZ; NRZI; BIPH-LEVEL(MANCHESTER)
最大数据传输速率：12.5 MBps外部数据总线宽度：32
JESD-30 代码：S-PQFP-G144JESD-609代码：e0
长度：20 mm低功率模式：YES
湿度敏感等级：3串行 I/O 数：4
端子数量：144最高工作温度：85 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
座面最大高度：1.6 mm最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：20 mmuPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches：1

DP83816AVNG-EX 数据手册

 浏览型号DP83816AVNG-EX的Datasheet PDF文件第4页浏览型号DP83816AVNG-EX的Datasheet PDF文件第5页浏览型号DP83816AVNG-EX的Datasheet PDF文件第6页浏览型号DP83816AVNG-EX的Datasheet PDF文件第8页浏览型号DP83816AVNG-EX的Datasheet PDF文件第9页浏览型号DP83816AVNG-EX的Datasheet PDF文件第10页 
Media Independent Interface (MII)  
LQFP Pin  
No(s)  
Symbol  
Dir  
Description  
COL  
28  
I
Collision Detect: The COL signal is asserted high asynchronously by the external  
PMD upon detection of a collision on the medium. It will remain asserted as long as  
the collision condition persists.  
CRS  
MDC  
29  
5
I
Carrier Sense: This signal is asserted high asynchronously by the external PMD  
upon detection of a non-idle medium.  
O
Management Data Clock: Clock signal with a maximum rate of 2.5 MHz used to  
transfer management data for the external PMD on the MDIO pin.  
MDIO  
4
I/O  
Management Data I/O: Bidirectional signal used to transfer management  
information for the external PMD. (See Section 3.12.4 for details on connections  
when MII is used.)  
RXCLK  
6
I
I
Receive Clock: A continuous clock, sourced by an external PMD device, that is  
recovered from the incoming data. During 100 Mb/s operation RXCLK is 25 MHz  
and during 10 Mb/s this is 2.5 MHz.  
RXD3/MA9,  
RXD2/MA8,  
RXD1/MA7,  
RXD0/MA6  
12,  
11,  
10,  
7
Receive Data: Sourced from an external PMD, that contains data aligned on nibble  
boundaries and are driven synchronous to RXCLK. RXD[3] is the most significant  
bit and RXD[0] is the least significant bit.  
BIOS ROM Address: During external BIOS ROM access, these signals become  
part of the ROM address.  
O
I
RXDV/MA11  
15  
Receive Data Valid: Indicates that the external PMD is presenting recovered and  
decoded nibbles on the RXD signals, and that RXCLK is synchronous to the  
recovered data in 100 Mb/s operation. This signal will encompass the frame,  
starting with the Start-of-Frame delimiter (JK) and excluding any End-of-Frame  
delimiter (TR).  
O
BIOS ROM Address: During external BIOS ROM access, this signal becomes part  
of the ROM address.  
RXER/MA10  
14  
I
Receive Error: Asserted high synchronously by the external PMD whenever it  
detects a media error and RXDV is asserted in 100 Mb/s operation.  
O
BIOS ROM Address: During external BIOS ROM access, this signal becomes part  
of the ROM address.  
RXOE  
13  
31  
O
I
Receive Output Enable: Used to disable an external PMD while the BIOS ROM is  
being accessed.  
TXCLK  
Transmit Clock: A continuous clock that is sourced by the external PMD. During  
100 Mb/s operation this is 25 MHz +/- 100 ppm. During 10 Mb/s operation this clock  
is 2.5 MHz +/- 100 ppm.  
TXD3/MA15,  
TXD2/MA14,  
TXD1/MA13,  
TXD0/MA12  
25,  
24,  
23,  
22  
O
Transmit Data: Signals which are driven synchronous to the TXCLK for  
transmission to the external PMD. TXD[3] is the most significant bit and TXD[0] is  
the least significant bit.  
BIOS ROM Address: During external BIOS ROM access, these signals become  
part of the ROM address.  
O
O
TXEN  
30  
Transmit Enable: This signal is synchronous to TXCLK and provides precise  
framing for data carried on TXD[3-0] for the external PMD. It is asserted when  
TXD[3-0] contains valid data to be transmitted.  
Note: MII is normally in TRI-STATE, unless enabled by CFG:EXT_PHY. See Section 4.2.2.  
7
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