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DP83820 PDF预览

DP83820

更新时间: 2024-02-22 04:40:08
品牌 Logo 应用领域
美国国家半导体 - NSC 网络接口控制器PC以太网局域网(LAN)标准
页数 文件大小 规格书
87页 1230K
描述
10/100/1000 Mb/s PCI Ethernet Network Interface Controller

DP83820 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:FQFP,针数:208
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.82Is Samacsys:N
地址总线宽度:32边界扫描:YES
总线兼容性:PCI最大时钟频率:25 MHz
最大数据传输速率:125 MBps外部数据总线宽度:32
JESD-30 代码:S-PQFP-G208长度:28 mm
低功率模式:YES串行 I/O 数:8
端子数量:208最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:FQFP封装形状:SQUARE
封装形式:FLATPACK, FINE PITCH认证状态:Not Qualified
座面最大高度:4.1 mm最大供电电压:1.95 V
最小供电电压:1.65 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:28 mmuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches:1

DP83820 数据手册

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PRELIMINARY  
February 2001  
DP83820 10/100/1000 Mb/s PCI Ethernet Network Interface  
Controller  
— Virtual LAN (VLAN) and long frame support. VLAN tag  
General Description  
insertion support for transmit packets. VLAN tag  
DP83820 is a single-chip 10/100/1000 Mb/s Ethernet  
Controller for the PCI bus. It is targeted at high-  
performance adapter cards and mother boards. The  
DP83820 fully implements the V2.2 66 MHz, 64-bit PCI bus  
interface for host communications with power management  
support. Packet descriptors and data are transferred via  
bus-mastering, reducing the burden on the host CPU. The  
DP83820 can support full duplex 10/100/1000 Mb/s  
transmission and reception.  
detection and removal for receive packets  
— 802.3x Full duplex flow control, including automatic  
transmission of Pause frames based on Rx FIFO  
thresholds  
— IPv.4 checksum task off-loading. Supports checksum  
generation and verification of IP, TCP, and UDP headers  
— 802.1D and 802.1Q priority queueing support. Supports  
multiple priority queues in both transmit and receive  
directions.  
— Extremely flexible Rx packet filtration including: single  
address perfect filter with MSb masking, broadcast,  
2,048 entry multicast/unicast hash table, deep packet  
pattern matching for up to 4 unique patterns.  
Features  
— IEEE 802.3 Compliant, 66/33 Mhz, 64/32-bit PCI V2.2  
MAC/BIU supports data rates from 1 Mb/s to 1000 Mb/s.  
This allows support for traditional 10 Mb/s Ethernet, 100  
Mb/s Fast Ethernet, as well as 1000 Mb/s Gigabit  
Ethernet.  
— Statistics gathered for support of RFC 1213 (MIB II),  
RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing  
CPU overhead for management.  
— Flexible, programmable Bus master - burst sizes of up to  
256 dwords (1024 bytes)  
— Internal 8 KB Transmit and 32 KB Receive data FIFOs  
— Supports Jumbo packets  
— BIU compliant with PC 97 and PC 98 Hardware Design  
Guides, PC 99 Hardware Design Guide draft, ACPI v1.0,  
PCI Power Management Specification v1, OnNow  
— Serial EEPROM port with auto-load of configuration data  
from EEPROM at power-on  
— Flash/PROM interface for remote boot support  
Device Class Power  
Management Reference  
Specification - Network Device Class v1.0a  
— Full Duplex support for 10/100/1000 Mb/s data rates  
— Wake on LAN (WOL) support compliant with PC98, — 208-pin PQFP package  
PC99, and OnNow, including directed packets, Magic  
Packet with SecureOn, ARP packets, pattern match  
packets, and Phy status change  
— Low power CMOS design  
— 3.3V powered I/Os with 5V tolerant inputs  
— JTAG Boundary Scan supported  
— GMII/MII provides IEEE 802.3 standard interface to  
support 10/100/1000 Mb/s physical layer devices  
— Ten-Bit Interface (TBI) for support of 1000BASE-X  
System Diagram  
PCI Bus  
MII  
DP83820  
GMII  
10/100/1000 Mb/s  
PHY  
EEPROM (optional)  
Boot ROM (optional)  
© 2001 National Semiconductor Corporation  
www.national.com  

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