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DP83816AVNG-EX PDF预览

DP83816AVNG-EX

更新时间： 2024-02-09 09:00:11
品牌 Logo 应用领域
美国国家半导体 - NSC 时钟局域网数据传输PC外围集成电路
页数 文件大小 规格书
106页 800K
描述
IC 4 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144, LQFP-144, Serial IO/Communication Controller

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DP83816AVNG-EX 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LFQFP,针数：144
Reach Compliance Code：compliantHTS代码：8542.31.00.01
风险等级：5.77地址总线宽度：32
边界扫描：NO总线兼容性：PCI
最大时钟频率：25 MHz数据编码/解码方法：NRZ; NRZI; BIPH-LEVEL(MANCHESTER)
最大数据传输速率：12.5 MBps外部数据总线宽度：32
JESD-30 代码：S-PQFP-G144JESD-609代码：e0
长度：20 mm低功率模式：YES
湿度敏感等级：3串行 I/O 数：4
端子数量：144最高工作温度：85 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
座面最大高度：1.6 mm最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：20 mmuPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches：1

DP83816AVNG-EX 数据手册

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100BASE-TX/10BASE-T Interface  
LQFP Pin  
No(s)  
Symbol  
Dir  
Description  
TPTDP, TPTDM  
54, 53  
A-O  
Transmit Data: Differential common output driver. This differential common output  
is configurable to either 10BASE-T or 100BASE-TX signaling:  
10BASE-T: Transmission of Manchester encoded 10BASE-T packet data as well as  
Link Pulses (including Fast Link Pulses for Auto-Negotiation purposes).  
100BASE-TX: Transmission of ANSI X3T12 compliant MLT-3 data.  
The DP83816-EX will automatically configure this common output driver for the  
proper signal type as a result of either forced configuration or Auto-Negotiation.  
TPRDP, TPRDM  
46, 45  
A-I  
Receive Data: Differential common input buffer. This differential common input can  
be configured to accept either 100BASE-TX or 10BASE-T signaling:  
10BASE-T: Reception of Manchester encoded 10BASE-T packet data as well as  
normal Link Pulses and Fast Link Pulses for Auto-Negotiation purposes.  
100BASE-TX: Reception of ANSI X3T12 compliant scrambled MLT-3 data.  
The DP83816-EX will automatically configure this common input buffer to accept  
the proper signal type as a result of either forced configuration or Auto-Negotiation.  
BIOS ROM/Flash Interface  
LQFP Pin  
Symbol  
MCSN  
No(s)  
Dir  
Description  
129  
O
BIOS ROM/Flash Chip Select: During a BIOS ROM/Flash access, this signal is  
used to select the ROM device.  
MD7, MD6, MD5,  
MD4/EEDO, MD3,  
MD2,  
MD1/CFGDISN,  
MD0  
141, 140, 139,  
138, 135,  
134,  
I/O  
O
BIOS ROM/Flash Data Bus: During a BIOS ROM/Flash access these signals are  
used to transfer data to or from the ROM/Flash device.  
MD[5:0] pins have internal weak pull ups.  
133,  
132  
MD6 and MD7 pins have internal weak pull downs.  
MA5,  
MA4/EECLK,  
MA3/EEDI,  
3,  
2,  
1,  
BIOS ROM/Flash Address: During a BIOS ROM/Flash access, these signals are  
used to drive the ROM/Flash address.  
MA2/LED100LNK,  
MA1/LED10LNK,  
MA0/LEDACT  
144,  
143,  
142  
MWRN  
131  
O
O
BIOS ROM/Flash Write: During a BIOS ROM/Flash access, this signal is used to  
enable data to be written to the Flash device.  
MRDN  
130  
BIOS ROM/Flash Read: During a BIOS ROM/Flash access, this signal is used to  
enable data to be read from the Flash device.  
Note: DP83816-EX supports NM27LV010 for the BIOS ROM interface device.  
Clock Interface  
LQFP Pin  
No(s)  
Symbol  
Dir  
Description  
X1  
17  
I
Crystal/Oscillator Input: This pin is the primary clock reference input for the  
DP83816-EX and must be connected to a 25 MHz 0.005% (50ppm) clock source.  
The DP83816-EX device supports either an external crystal resonator connected  
across pins X1 and X2, or an external CMOS-level oscillator source connected to  
pin X1 only.  
www.national.com  
8
1...567891011...106

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