June 2003
DP83816 10/100 Mb/s Integrated PCI Ethernet Media Access
Controller and Physical Layer (MacPHYTER-II™)
— Support for IEEE 802.3x Full duplex flow control
General Description
— Extremely flexible Rx packet filtration including: single
address perfect filter with MSb masking, broadcast, 512
entry multicast/unicast hash table, deep packet pattern
matching for up to 4 unique patterns
— Statistics gathered for support of RFC 1213 (MIB II),
RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing
CPU overhead for management
DP83816 is a single-chip 10/100 Mb/s Ethernet Controller
for the PCI bus. It is targeted at low-cost, high volume PC
motherboards, adapter cards, and embedded systems.
The DP83816 fully implements the V2.2 33 MHz PCI bus
interface for host communications with power management
support. Packet descriptors and data are transferred via
bus-mastering, reducing the burden on the host CPU. The
DP83816 can support full duplex 10/100 Mb/s transmission
and reception, with minimum interframe gap.
— Internal 2 KB Transmit and 2 KB Receive data FIFOs
— Serial EEPROM port with auto-load of configuration data
The DP83816 device is an integration of an enhanced
version of the National Semiconductor PCI MAC/BIU
(Media Access Controller/Bus Interface Unit) and a 3.3V
CMOS physical layer interface.
Features
from EEPROM at power-on
— Flash/PROM interface for remote boot support
— Fully integrated IEEE 802.3/802.3u 3.3V CMOS physical
layer
— IEEE 802.3 10BASE-T transceiver with integrated filters
— IEEE 802.3 Compliant, PCI V2.2 MAC/BIU supports — IEEE 802.3u 100BASE-TX transceiver
traditional data rates of 10 Mb/s Ethernet and 100 Mb/s
— Fully integrated ANSI X3.263 compliant TP-PMD
physical sublayer with adaptive equalization and
Baseline Wander compensation
Fast Ethernet (via internal phy)
— Bus master - burst sizes of up to 128 dwords (512 bytes)
— BIU compliant with PC 97 and PC 98 Hardware Design — IEEE 802.3u Auto-Negotiation - advertised features
Guides, PC 99 Hardware Design Guide draft, ACPI v1.0,
PCI Power Management Specification v1.1, OnNow
Device Class Power Management Reference
Specification - Network Device Class v1.0a
configurable via EEPROM
— Full Duplex support for 10 and 100 Mb/s data rates
— Single 25 MHz reference clock
— 144-pin LQFP package
— Low power 3.3V CMOS design with typical consumption
of 383 mW operating, 297 mW during WOL and 53 mW
during sleep mode
— Wake on LAN (WOL) support compliant with PC98,
PC99, SecureOn, and OnNow, including directed
packets, Magic Packet , VLAN packets, ARP packets,
pattern match packets, and Phy status change
— Clkrun function for PCI Mobile Design Guide
— Virtual LAN (VLAN) and long frame support
— IEEE 802.3u MII for connecting alternative external
Physical Layer Devices
— 3.3V signalling with 5V tolerant I/O.
System Diagram
PCI Bus
10/100 Twisted Pair
Isolation
DP83816
BIOS ROM EEPROM
(optional)
(optional)
®
TRI-STATE is a registered trademark of National Semiconductor Corporation.
MacPHYTER-II is a trademark of National Semiconductor Corporation.
is a trademark of Advanced Micro Devices, Inc.
©M2a0gi0c P3acNkeattional Semiconductor Corporation
www.national.com
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