DP83816AVNG-EXT

更新时间： 2024-01-31 09:17:57

品牌	Logo	应用领域
美国国家半导体 - NSC		控制器 PC 以太网局域网（LAN）标准
页数	文件大小	规格书
105页	1384K
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DP83816AVNG-EXT 数据手册

2.0 Pin Description (Continued)

PCI Bus Interface

LQFP Pin

Symbol

SERRN

No(s)

Dir

Description

I/O

System Error: This signal is asserted low by DP83816 during address parity errors

and system errors if enabled.

STOPN

TRDYN

I/O

Stop: This signal is asserted low by the target device to request the master device

to stop the current transaction.

Target Ready: As a master, this signal indicates that the target is ready for the data

during write operation and with the data during read operation. As a target, this

signal will be asserted low when the (target) device is ready to complete the current

data phase transaction. This signal is used in conjunction with the IRDYN signal.

Data transaction takes place at the rising edge of PCICLK when both IRDYN and

TRDYN are asserted low.

PMEN/

I/O

Power Management Event/Clock Run Function: This pin is a dual function pin.

The function of this pin is determined by the CLKRUN_EN bit 0 of the CLKRUN

Control and Status register (CCSR). Default operation of this pin is PMEN.

CLKRUNN

Power Management Event: This signal is asserted low by the DP83816 to indicate

that a power management event has occurred. For pin connection please refer to

Section 6.7.

Clock Run Function: In this mode, this pin is used to indicate when the PCICLK

will be stopped.

3VAUX

122

123

PCI Auxiliary Voltage Sense: This pin is used to sense the presence of a 3.3V

auxiliary supply in order to define the PME Support available. For pin connection

please refer to Section 6.7.

This pin has an internal weak pull down.

PWRGOOD

PCI bus power good: Connected to PCI bus 3.3V power, this pin is used to sense

the presence of PCI bus power during the D3 power management state.

This pin has an internal weak pull down.

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