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DM74S240 PDF预览

DM74S240

更新时间: 2024-02-23 19:07:02
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
4页 49K
描述
Octal 3-STATE Buffer/Line Driver/Line Receiver

DM74S240 技术参数

生命周期:Obsolete包装说明:SOP,
Reach Compliance Code:unknown风险等级:5.78
其他特性:MIN INPUT HYSTERESIS = 0.2V系列:S
JESD-30 代码:R-PDSO-G20长度:12.8 mm
负载电容(CL):45 pF逻辑集成电路类型:BUS DRIVER
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
最大电源电流(ICC):150 mA传播延迟(tpd):10 ns
认证状态:Not Qualified座面最大高度:2.65 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.5 mm
Base Number Matches:1

DM74S240 数据手册

 浏览型号DM74S240的Datasheet PDF文件第2页浏览型号DM74S240的Datasheet PDF文件第3页浏览型号DM74S240的Datasheet PDF文件第4页 
August 1986  
Revised May 2000  
DM74S240 DM74S241 DM74S244  
Octal 3-STATE Buffer/Line Driver/Line Receiver  
General Description  
Features  
These buffers/line drivers are designed to improve both the  
performance and PC board density of 3-STATE buffers/  
drivers employed as memory-address drivers, clock driv-  
ers, and bus-oriented transmitters/receivers. Featuring 400  
mV of hysteresis at each low current PNP data line input,  
they provide improved noise rejection and high fanout out-  
puts, and can be used to drive terminated lines down to  
133.  
3-STATE outputs drive bus lines directly  
PNP inputs reduce DC loading on bus lines  
Hysteresis at data inputs improves noise margins  
Typical IOL (sink current)  
64 mA  
Typical IOH (source current) 15 mA  
Typical propagation delay times  
Inverting  
4.5 ns  
Noninverting 6 ns  
Typical enable/disable times 9 ns  
Typical power dissipation (enabled)  
Inverting  
450 mW  
Noninverting 538 mW  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74S240N  
DM74S241N  
DM74S244N  
N20A  
N20A  
N20A  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Connection Diagrams  
DM74S241N  
DM74S240N  
DM74S244N  
© 2000 Fairchild Semiconductor Corporation  
DS006478  
www.fairchildsemi.com  

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