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DM74S241N PDF预览

DM74S241N

更新时间: 2024-01-22 23:59:57
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
4页 49K
描述
Octal 3-STATE Buffer/Line Driver/Line Receiver

DM74S241N 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:DIP, DIP20,.3Reach Compliance Code:unknown
风险等级:5.92Is Samacsys:N
控制类型:ENABLE LOW/HIGHJESD-30 代码:R-PDIP-T20
JESD-609代码:e0逻辑集成电路类型:BUS DRIVER
最大I(ol):0.064 A位数:4
功能数量:2端子数量:20
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:5 V
最大电源电流(ICC):180 mAProp。Delay @ Nom-Sup:9 ns
认证状态:Not Qualified子类别:Bus Driver/Transceivers
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
Base Number Matches:1

DM74S241N 数据手册

 浏览型号DM74S241N的Datasheet PDF文件第2页浏览型号DM74S241N的Datasheet PDF文件第3页浏览型号DM74S241N的Datasheet PDF文件第4页 
August 1986  
Revised May 2000  
DM74S240 DM74S241 DM74S244  
Octal 3-STATE Buffer/Line Driver/Line Receiver  
General Description  
Features  
These buffers/line drivers are designed to improve both the  
performance and PC board density of 3-STATE buffers/  
drivers employed as memory-address drivers, clock driv-  
ers, and bus-oriented transmitters/receivers. Featuring 400  
mV of hysteresis at each low current PNP data line input,  
they provide improved noise rejection and high fanout out-  
puts, and can be used to drive terminated lines down to  
133.  
3-STATE outputs drive bus lines directly  
PNP inputs reduce DC loading on bus lines  
Hysteresis at data inputs improves noise margins  
Typical IOL (sink current)  
64 mA  
Typical IOH (source current) 15 mA  
Typical propagation delay times  
Inverting  
4.5 ns  
Noninverting 6 ns  
Typical enable/disable times 9 ns  
Typical power dissipation (enabled)  
Inverting  
450 mW  
Noninverting 538 mW  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74S240N  
DM74S241N  
DM74S244N  
N20A  
N20A  
N20A  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Connection Diagrams  
DM74S241N  
DM74S240N  
DM74S244N  
© 2000 Fairchild Semiconductor Corporation  
DS006478  
www.fairchildsemi.com  

DM74S241N 替代型号

型号 品牌 替代类型 描述 数据表
SN74S241N TI

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