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DM74S195 PDF预览

DM74S195

更新时间: 2024-11-29 04:39:03
品牌 Logo 应用领域
美国国家半导体 - NSC 移位寄存器
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6页 132K
描述
Shift Registers

DM74S195 数据手册

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June 1989  
DM54S195/DM74S195 4-Bit Parallel Access  
Shift Registers  
General Description  
These 4-bit registers feature parallel inputs, parallel outputs,  
J-K serial inputs, shift/load control input, and a direct over-  
riding clear. All inputs are buffered to lower the input drive  
requirements. The registers have two modes of operation:  
The high-performance S195, with a 105 MHz typical shift  
frequency, is particularly attractive for very high-speed data  
processing systems. In most cases existing systems can be  
upgraded merely by using this Schottky-clamped shift regis-  
ter.  
Parallel (broadside) load  
Shift (in the direction Q toward Q )  
D
A
Features  
Y
Parallel loading is accomplished by applying the four bits of  
data and taking the shift/load control input low. The data is  
loaded into the associated flip-flop and appears at the out-  
puts after the positive transition of the clock input. During  
loading, serial data flow is inhibited.  
Synchronous parallel load  
Y
Positive-edge-triggered clocking  
Y
Parallel inputs and outputs from each flip-flop  
Y
Direct overriding clear  
Y
J and K inputs to first stage  
Shifting is accomplished synchronously when the shift/load  
control input is high. Serial data for this mode is entered at  
the J-K inputs. These inputs permit the first stage to perform  
as a J-K, D, or T-type flip-flop as shown in the truth table.  
Y
Complementary outputs from last stage  
Y
For use in high-performance:  
accumulators/processors  
serial-to-parallel, parallel-to-serial converters  
Y
Typical clock frequency 105 MHz  
Y
Typical power dissipation 350 mW  
Connection Diagram  
Dual-In-Line Package  
TL/F/6476–1  
Order Number DM54S195J or DM74S195N  
See NS Package Number J16A or N16E  
C
1995 National Semiconductor Corporation  
TL/F/6476  
RRD-B30M105/Printed in U. S. A.  

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