5秒后页面跳转
DM74S174N PDF预览

DM74S174N

更新时间: 2024-11-08 22:54:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
5页 59K
描述
Hex/Quad D Flip-Flop with Clear

DM74S174N 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.48
系列:SJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.305 mm
逻辑集成电路类型:D FLIP-FLOP最大I(ol):0.02 A
位数:6功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):144 mA
Prop。Delay @ Nom-Sup:21 ns传播延迟(tpd):21 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:FF/Latches最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:110 MHzBase Number Matches:1

DM74S174N 数据手册

 浏览型号DM74S174N的Datasheet PDF文件第2页浏览型号DM74S174N的Datasheet PDF文件第3页浏览型号DM74S174N的Datasheet PDF文件第4页浏览型号DM74S174N的Datasheet PDF文件第5页 
August 1986  
Revised April 2000  
DM74S174 DM74S175  
Hex/Quad D Flip-Flop with Clear  
General Description  
Features  
These positive-edge-triggered flip-flops utilize TTL circuitry  
to implement D-type flip-flop logic. All have a direct clear  
input, and the quad (DM74S175) versions feature comple-  
mentary outputs from each flip-flop.  
DM74S174 contain six flip-flops with single-rail outputs.  
DM74S175 contain four flip-flops with double-rail out-  
puts.  
Buffered clock and direct clear inputs  
Individual data input to each flip-flop  
Applications include:  
Information at the D inputs meeting the setup time require-  
ments is transferred to the Q outputs on the positive-going  
edge of the clock pulse. Clock triggering occurs at a partic-  
ular voltage level and is not directly related to the transition  
time of the positive-going pulse. When the clock input is at  
either the HIGH or LOW level, the D input signal has no  
effect at the output.  
Buffer/storage registers  
Shift registers  
Pattern generators  
Typical clock frequency 110 MHz  
Typical power dissipation per flip-flop 75mW  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74S174N  
DM74S175N  
N16E  
N16E  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Connection Diagrams  
DM74S174  
DM74S175  
© 2000 Fairchild Semiconductor Corporation  
DS006472  
www.fairchildsemi.com  

DM74S174N 替代型号

型号 品牌 替代类型 描述 数据表
SN74S174NE4 TI

类似代替

HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SN74S174N TI

类似代替

HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

与DM74S174N相关器件

型号 品牌 获取价格 描述 数据表
DM74S174N/A+ TI

获取价格

IC,FLIP-FLOP,HEX,D TYPE,S-TTL,DIP,16PIN,PLASTIC
DM74S174N/B+ TI

获取价格

IC,FLIP-FLOP,HEX,D TYPE,S-TTL,DIP,16PIN,PLASTIC
DM74S175N FAIRCHILD

获取价格

Hex/Quad D Flip-Flop with Clear
DM74S175N TI

获取价格

S SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
DM74S175N/A+ TI

获取价格

IC,FLIP-FLOP,QUAD,D TYPE,S-TTL,DIP,16PIN,PLASTIC
DM74S175N/B+ TI

获取价格

IC,FLIP-FLOP,QUAD,D TYPE,S-TTL,DIP,16PIN,PLASTIC
DM74S181 NSC

获取价格

ARITHMETIC LOGIC UNIT/FUNCTION GENERATORS
DM74S181J NSC

获取价格

暂无描述
DM74S181J/A+ ETC

获取价格

Fixed Point ALU
DM74S181N NSC

获取价格

ARITHMETIC LOGIC UNIT/FUNCTION GENERATORS