DM74S161

更新时间： 2024-11-27 22:54:35

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		计数器
页数	文件大小	规格书
7页	83K
描述
Synchronous 4-Bit Binary Counters

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数据手册

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DM74S161 数据手册

August 1986

Revised April 2000

DM74S161 • DM74S163

Synchronous 4-Bit Binary Counters

The carry look-ahead circuitry provides for cascading

counters for n-bit synchronous applications without addi-

tional gating. Instrumental in accomplishing this function

are two count-enable inputs and a ripple carry output. Both

count-enable inputs (P and T) must be HIGH to count, and

input T is fed forward to enable the ripple carry output. The

ripple carry output thus enabled will produce a HIGH-level

output pulse with a duration approximately equal to the

HIGH-level portion of the Q_Aoutput. This HIGH-level over-

General Description

These synchronous, presettable counters feature an inter-

nal carry look-ahead for application in high-speed counting

designs. They are 4-bit binary counters. The carry output is

decoded by means of a NOR gate, thus preventing spikes

during the normal counting mode of operation. Synchro-

nous operation is provided by having all flip-flops clocked

simultaneously so that the outputs change coincident with

each other when so instructed by the count enable inputs

and internal gating. This mode of operation eliminates the

output counting spikes which are normally associated with

asynchronous (ripple clock) counters. A buffered clock

input triggers the four flip-flops on the rising (positive-

going) edge of the clock input waveform.

flow ripple carry pulse can be used to enable successive

cascaded stages.

Features

■ Synchronously programmable

■ Internal look-ahead for fast counting

■ Carry output for n-bit cascading

■ Synchronous counting

These counters are fully programmable; that is, the outputs

may be preset to either level. As presetting is synchronous,

setting up a LOW level at the load input disables the

counter and causes the outputs to agree with the setup

data after the next clock pulse regardless of the levels of

the enable input.

■ Load control line

■ Diode-clamped inputs

Ordering Code:

Order Number Package Number

Package Description

DM74S161N

DM74S163N

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Connection Diagram

DS006471

www.fairchildsemi.com

12 3 4 5 6 7

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与DM74S161相关器件

型号	品牌	获取价格	描述	数据表
DM74S161J	NSC	获取价格	IC,COUNTER,UP,4-BIT BINARY,S-TTL,DIP,16PIN,CERAMIC
DM74S161J/A+	ETC	获取价格	Synchronous Up Counter
DM74S161N	NSC	获取价格	SYNCHRONOUS 4-BIT BINARY COUNTERS
DM74S161N	FAIRCHILD	获取价格	Synchronous 4-Bit Binary Counters
DM74S161N/A+	ETC	获取价格	Synchronous Up Counter
DM74S161N/B+	ETC	获取价格	Synchronous Up Counter
DM74S162J	NSC	获取价格	IC,COUNTER,UP,DECADE,S-TTL,DIP,16PIN,CERAMIC
DM74S162J/A+	ETC	获取价格	Synchronous Up Counter
DM74S162N	ETC	获取价格	Synchronous Up Counter
DM74S162N/A+	ETC	获取价格	Synchronous Up Counter