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DM74S153N PDF预览

DM74S153N

更新时间: 2024-11-25 22:54:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 解复用器逻辑集成电路光电二极管
页数 文件大小 规格书
4页 50K
描述
Dual 1-of-4 Line Data Selector/Multiplexer

DM74S153N 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.28
系列:SJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.305 mm
逻辑集成电路类型:MULTIPLEXER最大I(ol):0.02 A
功能数量:2输入次数:4
输出次数:1端子数量:16
最高工作温度:70 °C最低工作温度:
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):70 mAProp。Delay @ Nom-Sup:12 ns
传播延迟(tpd):21 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Multiplexer/Demultiplexers
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

DM74S153N 数据手册

 浏览型号DM74S153N的Datasheet PDF文件第2页浏览型号DM74S153N的Datasheet PDF文件第3页浏览型号DM74S153N的Datasheet PDF文件第4页 
August 1986  
Revised April 2000  
DM74S153  
Dual 1-of-4 Line Data Selector/Multiplexer  
General Description  
Features  
Each of these data selectors/multiplexers contains invert-  
ers and drivers to supply fully complementary, on-chip,  
binary decoding data selection to the AND-OR-invert  
gates. Separate strobe inputs are provided for each of the  
two four-line sections.  
Permits multiplexing from N lines to 1 line  
Performs parallel-to-serial conversion  
Strobe (enable) line provided for cascading (N lines to  
n lines)  
High fan-out, low-impedance, totem-pole outputs  
Typical average propagation delay times  
From data  
6 ns  
From strobe 9.5 ns  
From select 12 ns  
Typical power dissipation 225 mW  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74S153N  
N16E  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Connection Diagram  
Function Table  
Select  
Data Inputs  
Strobe  
Output  
Inputs  
B
X
L
A
X
L
C0  
X
L
C1  
X
X
X
L
C2  
X
X
X
X
X
L
C3  
X
X
X
X
X
X
X
L
G
H
L
L
L
L
L
L
L
L
Y
L
L
L
L
H
X
X
X
X
X
X
H
L
L
H
H
L
L
H
X
X
X
X
H
L
H
H
H
H
L
H
X
X
H
L
H
H
H
H
Select inputs A and B are common to both sections.  
H = HIGH Level  
L = LOW Level  
X = Don’t Care  
© 2000 Fairchild Semiconductor Corporation  
DS006469  
www.fairchildsemi.com  

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