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DM74S139N PDF预览

DM74S139N

更新时间: 2024-11-25 22:54:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 解码器驱动器解复用器逻辑集成电路光电二极管
页数 文件大小 规格书
5页 58K
描述
Decoder/Demultiplexer

DM74S139N 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:0.300 INCH, PLASTIC, MS-001, DIP-16
针数:16Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.46Is Samacsys:N
系列:SJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.305 mm
逻辑集成电路类型:OTHER DECODER/DRIVER最大I(ol):0.02 A
功能数量:2端子数量:16
最高工作温度:70 °C最低工作温度:
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED最大电源电流(ICC):90 mA
Prop。Delay @ Nom-Sup:15 ns传播延迟(tpd):15 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Decoder/Drivers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

DM74S139N 数据手册

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August 1986  
Revised April 2000  
DM74S138 DM74S139  
Decoder/Demultiplexer  
General Description  
Features  
These Schottky-clamped circuits are designed to be used  
in high-performance memory-decoding or data-routing  
applications, requiring very short propagation delay times.  
In high-performance memory systems these decoders can  
be used to minimize the effects of system decoding. When  
used with high-speed memories, the delay times of these  
decoders are usually less than the typical access time of  
the memory. This means that the effective system delay  
introduced by the decoder is negligible.  
Designed specifically for high speed:  
Memory decoders  
Data transmission systems  
DM74S138 3-to-8-line decoders incorporates 3 enable  
inputs to simplify cascading and/or data reception  
DM74S139 contains two fully independent 2-to-4-line  
decoders/demultiplexers  
Schottky clamped for high performance  
Typical propagation delay time (3 levels of logic)  
DM74S138 8 ns  
The DM74S138 decodes one-of-eight lines, based upon  
the conditions at the three binary select inputs and the  
three enable inputs. Two active-LOW and one active-HIGH  
enable inputs reduce the need for external gates or invert-  
ers when expanding. A 24-line decoder can be imple-  
mented with no external inverters, and a 32-line decoder  
requires only one inverter. An enable input can be used as  
a data input for demultiplexing applications.  
DM74S139 7.5 ns  
Typical power dissipation  
DM74S138 245 mW  
DM74S139 300 mW  
The DM74S139 comprises two separate two-line-to-four-  
line decoders in a single package. The active-LOW enable  
input can be used as a data line in demultiplexing applica-  
tions.  
All of these decoders/demultiplexers feature fully buffered  
inputs, presenting only one normalized load to its driving  
circuit. All inputs are clamped with high-performance  
Schottky diodes to suppress line-ringing and simplify sys-  
tem design.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74S138N  
DM74S139N  
N16E  
N16E  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
© 2000 Fairchild Semiconductor Corporation  
DS006466  
www.fairchildsemi.com  

DM74S139N 替代型号

型号 品牌 替代类型 描述 数据表
SN74S139AN TI

类似代替

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SN74S139ANE4 TI

功能相似

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

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