DM74S138CW

更新时间： 2024-11-26 13:07:23

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		解码器解复用器
页数	文件大小	规格书
5页	58K
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数据手册

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DM74S138CW 数据手册

August 1986

Revised April 2000

DM74S138 • DM74S139

Decoder/Demultiplexer

General Description

Features

These Schottky-clamped circuits are designed to be used

in high-performance memory-decoding or data-routing

applications, requiring very short propagation delay times.

In high-performance memory systems these decoders can

be used to minimize the effects of system decoding. When

used with high-speed memories, the delay times of these

decoders are usually less than the typical access time of

the memory. This means that the effective system delay

introduced by the decoder is negligible.

■ Designed specifically for high speed:

Memory decoders

Data transmission systems

■ DM74S138 3-to-8-line decoders incorporates 3 enable

inputs to simplify cascading and/or data reception

■ DM74S139 contains two fully independent 2-to-4-line

decoders/demultiplexers

■ Schottky clamped for high performance

■ Typical propagation delay time (3 levels of logic)

DM74S138 8 ns

The DM74S138 decodes one-of-eight lines, based upon

the conditions at the three binary select inputs and the

three enable inputs. Two active-LOW and one active-HIGH

enable inputs reduce the need for external gates or invert-

ers when expanding. A 24-line decoder can be imple-

mented with no external inverters, and a 32-line decoder

requires only one inverter. An enable input can be used as

a data input for demultiplexing applications.

DM74S139 7.5 ns

■ Typical power dissipation

DM74S138 245 mW

DM74S139 300 mW

The DM74S139 comprises two separate two-line-to-four-

line decoders in a single package. The active-LOW enable

input can be used as a data line in demultiplexing applica-

tions.

All of these decoders/demultiplexers feature fully buffered

inputs, presenting only one normalized load to its driving

circuit. All inputs are clamped with high-performance

Schottky diodes to suppress line-ringing and simplify sys-

tem design.

Ordering Code:

Order Number Package Number

Package Description

DM74S138N

DM74S139N

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

DS006466

www.fairchildsemi.com

12 3 4 5

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与DM74S138CW相关器件

型号	品牌	获取价格	描述	数据表
DM74S138J	TI	获取价格	IC,DECODER/DEMUX,3-TO-8-LINE,S-TTL,DIP,16PIN,CERAMIC
DM74S138J/A+	ETC	获取价格	3-To-8-Line Demultiplexer
DM74S138N	FAIRCHILD	获取价格	Decoder/Demultiplexer
DM74S138N	TI	获取价格	S SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDIP16, PLASTIC, DIP-16
DM74S138N/A+	TI	获取价格	IC,DECODER/DEMUX,3-TO-8-LINE,S-TTL,DIP,16PIN,PLASTIC
DM74S138N/B+	TI	获取价格	IC,DECODER/DEMUX,3-TO-8-LINE,S-TTL,DIP,16PIN,PLASTIC
DM74S139	FAIRCHILD	获取价格	Decoder/Demultiplexer
DM74S139J	TI	获取价格	IC,DECODER/DEMUX,2-TO-4-LINE,S-TTL,DIP,16PIN,CERAMIC
DM74S139J	ROCHESTER	获取价格	Decoder/Driver
DM74S139J/A+	TI	获取价格	IC,DECODER/DEMUX,2-TO-4-LINE,S-TTL,DIP,16PIN,CERAMIC