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DM74LS42M

更新时间: 2024-11-24 23:00:43
品牌 Logo 应用领域
美国国家半导体 - NSC 解码器
页数 文件大小 规格书
6页 131K
描述
Decimal Decoders

DM74LS42M 数据手册

 浏览型号DM74LS42M的Datasheet PDF文件第2页浏览型号DM74LS42M的Datasheet PDF文件第3页浏览型号DM74LS42M的Datasheet PDF文件第4页浏览型号DM74LS42M的Datasheet PDF文件第5页浏览型号DM74LS42M的Datasheet PDF文件第6页 
June 1989  
54LS42/DM54LS42/DM74LS42 BCD/Decimal Decoders  
General Description  
Features  
Y
Diode clamped inputs  
These BCD-to-decimal decoders consist of eight inverters  
and ten, four-input NAND gates. The inverters are connect-  
ed in pairs to make BCD input data available for decoding  
by the NAND gates. Full decoding of input logic ensures  
that all outputs remain off for all invalid (1015) input condi-  
tions.  
Y
Also for applications as 4-line-to-16-line decoders; 3-  
line-to-8-line decoders  
Y
Y
All outputs are high for invalid input conditions  
Alternate Military/Aerospace device (54LS42) is avail-  
able. Contact a National Semiconductor Sales Office/  
Distributor for specifications.  
Connection Diagram  
Function Table  
Dual-In-Line Package  
BCD Inputs  
No.  
Decimal Outputs  
D
C
B
A
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
L
H
H
H
H
H
L
H
H
L
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
5
6
7
8
9
L
L
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
L
H
H
H
L
H
H
H
H
L
L
H
L
H
H
H
H
H
H
H
L
L
H
H
I
H
H
H
H
H
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
N
V
A
L
I
TL/F/6365–1  
Order Number 54LS42DMQB, 54LS42FMQB,  
H
H
H
H
L
H
L
DM54LS42J, DM54LS42W, DM74LS42M or DM74LS42N  
See NS Package Number J16A, M16A, N16E or W16A  
H
H
H
D
e
e
H
L
High Level  
Low Level  
Logic Diagram  
TL/F/6365–2  
C
1995 National Semiconductor Corporation  
TL/F/6365  
RRD-B30M105/Printed in U. S. A.  

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