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DM74LS299WM PDF预览

DM74LS299WM

更新时间: 2024-02-20 22:12:44
品牌 Logo 应用领域
美国国家半导体 - NSC 存储
页数 文件大小 规格书
8页 169K
描述
8-Input Universal Shift/Storage Register with Common Parallel I/O Pins

DM74LS299WM 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Contact Manufacturer零件包装代码:SOIC
包装说明:SOP,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.85其他特性:HOLD MODE; COMMON I/O PINS; GATED OUTPUT CONTROL
计数方向:BIDIRECTIONAL系列:LS
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:12.8 mm逻辑集成电路类型:PARALLEL IN PARALLEL OUT
位数:8功能数量:1
端子数量:20最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):35 ns认证状态:Not Qualified
座面最大高度:2.65 mm最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.5 mm
最小 fmax:35 MHzBase Number Matches:1

DM74LS299WM 数据手册

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June 1992  
DM54LS299/DM74LS299  
8-Input Universal Shift/Storage Register  
with Common Parallel I/O Pins  
General Description  
The ’LS299 is an 8-bit universal shift/storage register with  
Features  
Y
Common I/O for reduced pin count  
Y
TRI-STATE outputs. Four modes of operation are possi-  
Four operation modes: shift left, shift right, load and  
store  
É
ble: hold (store), shift left, shift right and load data. The par-  
allel load inputs and flip-flop outputs are multiplexed to re-  
duce the total number of package pins. Separate outputs  
are provided for flip-flops Q0 and Q7 to allow easy cascad-  
ing. A separate active LOW Master Reset is used to reset  
the register.  
Y
Y
Separate shift right serial input and shift left serial input  
for easy cascading  
TRI-STATE outputs for bus oriented applications  
Connection Diagram  
Dual-In-Line Package  
TL/F/9827–1  
Order Number DM54LS299E, DM54LS299J, DM54LS299W,  
DM74LS299WM or DM74LS299N  
See NS Package Number E20A, J20A, M20B, N20A or W20A  
Pin Names  
Description  
CP  
Clock Pulse Input (Active Rising Edge)  
Serial Data Input for Right Shift  
Serial Data Input for Left Shift  
Mode Select Inputs  
D
D
S0  
S7  
S0, S1  
MR  
Asynchronous Master Reset Input  
(Active LOW)  
OE1, OE2  
I/O0I/O7  
Q0Q7  
TRI-STATE Output Enable Inputs  
(Active LOW)  
Parallel Data Inputs or TRI-STATE  
Parallel Outputs  
Serial Outputs  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/9827  
RRD-B30M115/Printed in U. S. A.  

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