DM74AS646

更新时间： 2024-09-30 22:56:51

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		总线收发器
页数	文件大小	规格书
8页	85K
描述
Octal Bus Transceiver and Register

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中文翻译

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数据手册

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DM74AS646 数据手册

October 1986

Revised March 2000

DM74AS646 • DM74AS648

Octal Bus Transceiver and Register

General Description

Features

This device incorporates an octal bus transceiver and an

octal D-type register configured to enable multiplexed

transmission of data from bus to bus or internal register to

bus.

■ Switching specifications at 50 pF

■ Switching specifications guaranteed over full tempera-

ture and V_CCrange

■ Advanced oxide-isolated, ion-implanted Schottky TTL

This bus transceiver features totem-pole 3-STATE outputs

designed specifically for driving highly-capacitive or rela-

tively low-impedance loads. The high-impedance third

state and increased high-logic-level drive provide this

device with the capability of being connected directly to and

driving the bus lines in a bus-organized system without

need for interface or pull-up components. It is particularly

attractive for implementing buffer registers, I/O ports, bidi-

rectional bus drivers, and working registers.

process

■ Functionally and pin-for-pin compatible with LS TTL

counterpart

■ 3-STATE buffer-type outputs drive bus lines directly

The registers in the DM74AS646, DM74AS648 are edge-

triggered D-type flip-flops. On the positive transition of the

clock (CAB or CBA), the input bus data is stored.

The SAB and SBA control pins are provided to select

whether real-time data or stored data is transferred. A LOW

input level selects real-time data, and a HIGH level selects

stored data. The select controls have a “make before

break” configuration to eliminate a glitch which would nor-

mally occur in a typical multiplexer during the transition

between stored and real-time data.

The enable G and direction control pins provide four modes

of operation; real-time data transfer from bus A to B, real-

time data transfer from bus B to A, real-time bus A and/or B

data transfer to internal storage, or internal store data

transfer to bus A or B.

When the enable G pin is LOW, the direction pin selects

which bus receives data. When the enable G pin is HIGH,

both buses become disabled yet their input function is still

enabled.

Ordering Code:

Order Number Package Number

Package Description

DM74AS646WM

DM74AS646NT

DM74AS648WM

DM74AS648NT

M24B

N24C

M24B

N24C

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

DS006324

www.fairchildsemi.com

12 3 4 5 6 7 8

中文翻译

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与DM74AS646相关器件

型号	品牌	获取价格	描述	数据表
DM74AS646J/A+	ETC	获取价格	Single 8-bit Bus Transceiver
DM74AS646N/A+	ETC	获取价格	Single 8-bit Bus Transceiver
DM74AS646N/B+	ETC	获取价格	Single 8-bit Bus Transceiver
DM74AS646NT	FAIRCHILD	获取价格	Octal Bus Transceiver and Register
DM74AS646WM	FAIRCHILD	获取价格	Octal Bus Transceiver and Register
DM74AS646WMX	ETC	获取价格	Single 8-bit Bus Transceiver
DM74AS648J/A+	ETC	获取价格	Single 8-Bit Inverting Bus Transceiver
DM74AS648N/A+	ETC	获取价格	Single 8-Bit Inverting Bus Transceiver
DM74AS648N/B+	ETC	获取价格	Single 8-Bit Inverting Bus Transceiver
DM74AS648NT	FAIRCHILD	获取价格	Octal Bus Transceiver and Register

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