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DM74AS646WM

更新时间： 2024-11-14 22:56:51
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 85K
描述
Octal Bus Transceiver and Register

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中文翻译

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DM74AS646WM 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：0.300 INCH, MS-013, SOIC-24
针数：24Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.37
Is Samacsys：N其他特性：WITH DIRECTION CONTROL
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：ASJESD-30 代码：R-PDSO-G24
JESD-609代码：e3长度：15.4 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.048 A
湿度敏感等级：1位数：8
功能数量：1端口数量：2
端子数量：24最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP24,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：5 V
最大电源电流（ICC）：211 mAProp。Delay @ Nom-Sup：9 ns
传播延迟（tpd）：9 ns认证状态：Not Qualified
座面最大高度：2.65 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：7.5 mm
Base Number Matches：1

DM74AS646WM 数据手册

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October 1986  
Revised March 2000  
DM74AS646 • DM74AS648  
Octal Bus Transceiver and Register  
General Description  
Features  
This device incorporates an octal bus transceiver and an  
octal D-type register configured to enable multiplexed  
transmission of data from bus to bus or internal register to  
bus.  
■ Switching specifications at 50 pF  
■ Switching specifications guaranteed over full tempera-  
ture and VCC range  
■ Advanced oxide-isolated, ion-implanted Schottky TTL  
This bus transceiver features totem-pole 3-STATE outputs  
designed specifically for driving highly-capacitive or rela-  
tively low-impedance loads. The high-impedance third  
state and increased high-logic-level drive provide this  
device with the capability of being connected directly to and  
driving the bus lines in a bus-organized system without  
need for interface or pull-up components. It is particularly  
attractive for implementing buffer registers, I/O ports, bidi-  
rectional bus drivers, and working registers.  
process  
■ Functionally and pin-for-pin compatible with LS TTL  
counterpart  
■ 3-STATE buffer-type outputs drive bus lines directly  
The registers in the DM74AS646, DM74AS648 are edge-  
triggered D-type flip-flops. On the positive transition of the  
clock (CAB or CBA), the input bus data is stored.  
The SAB and SBA control pins are provided to select  
whether real-time data or stored data is transferred. A LOW  
input level selects real-time data, and a HIGH level selects  
stored data. The select controls have a “make before  
break” configuration to eliminate a glitch which would nor-  
mally occur in a typical multiplexer during the transition  
between stored and real-time data.  
The enable G and direction control pins provide four modes  
of operation; real-time data transfer from bus A to B, real-  
time data transfer from bus B to A, real-time bus A and/or B  
data transfer to internal storage, or internal store data  
transfer to bus A or B.  
When the enable G pin is LOW, the direction pin selects  
which bus receives data. When the enable G pin is HIGH,  
both buses become disabled yet their input function is still  
enabled.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74AS646WM  
DM74AS646NT  
DM74AS648WM  
DM74AS648NT  
M24B  
N24C  
M24B  
N24C  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 2000 Fairchild Semiconductor Corporation  
DS006324  
www.fairchildsemi.com  
12345678

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DM74AS646WM 替代型号

型号 品牌 替代类型 描述 数据表
SN74AS646DW TI

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