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DM74ALS541SJX_NL PDF预览

DM74ALS541SJX_NL

更新时间: 2024-11-04 21:13:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
6页 62K
描述
Bus Driver, 1-Func, 8-Bit, True Output, TTL, PDSO20,

DM74ALS541SJX_NL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:SOP, SOP20,.3Reach Compliance Code:compliant
风险等级:5.84控制类型:ENABLE LOW
JESD-30 代码:R-PDSO-G20逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A位数:8
功能数量:1端子数量:20
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
电源:5 V最大电源电流(ICC):25 mA
Prop。Delay @ Nom-Sup:14 ns认证状态:Not Qualified
子类别:Bus Driver/Transceivers标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

DM74ALS541SJX_NL 数据手册

 浏览型号DM74ALS541SJX_NL的Datasheet PDF文件第2页浏览型号DM74ALS541SJX_NL的Datasheet PDF文件第3页浏览型号DM74ALS541SJX_NL的Datasheet PDF文件第4页浏览型号DM74ALS541SJX_NL的Datasheet PDF文件第5页浏览型号DM74ALS541SJX_NL的Datasheet PDF文件第6页 
October 1986  
Revised February 2000  
DM74ALS541  
Octal Buffer and Line Driver with 3-STATE Outputs  
General Description  
Features  
This octal buffer and line driver is designed to have the per-  
formance of the DM74ALS240A series and, at the same  
time, offer a pinout with inputs and outputs on opposite  
sides of the package. This arrangement greatly enhances  
circuit board layout. The 3-STATE control gate is a 2-input  
NOR such that if either G1 or G2 is HIGH, all eight outputs  
are in the high impedance state.  
Advanced oxide-isolated ion-implanted Schottky TTL  
process  
Switching performance is guaranteed over full tempera-  
ture and VCC supply range  
Data flow-thru pinout (all inputs on opposite side from  
outputs)  
P-N-P Inputs reduce DC loading  
Ordering Code:  
Order Number  
DM74ALS541WM  
DM74ALS541SJ  
DM74ALS541N  
Package Number Package Description  
M20B  
M20D  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Input  
Output  
G1  
H
X
G2  
X
A
X
X
L
Y
Hi-Z  
Hi-Z  
L
H
L
L
L
L
H
H
H = HIGH Logic Level  
L = LOW Logic Level  
X = Don't Care (Either LOW or HIGH Logic Level)  
Hi-Z = High Impedance (OFF) State  
© 2000 Fairchild Semiconductor Corporation  
DS009171  
www.fairchildsemi.com  

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