DM7476J

更新时间： 2024-11-13 13:07:23

品牌	Logo	应用领域
美国国家半导体 - NSC		触发器
页数	文件大小	规格书
4页	111K
描述
IC,FLIP-FLOP,DUAL,J/K TYPE,STD-TTL,DIP,16PIN,CERAMIC

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中文翻译

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技术参数
数据手册

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DM7476J 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP, DIP16,.3	Reach Compliance Code：	compliant
风险等级：	5.81	Is Samacsys：	N
JESD-30 代码：	R-XDIP-T16	JESD-609代码：	e0
逻辑集成电路类型：	J-K FLIP-FLOP	最大频率@ Nom-Sup：	15000000 Hz
最大I（ol）：	0.016 A	功能数量：	2
端子数量：	16	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	CERAMIC
封装代码：	DIP	封装等效代码：	DIP16,.3
封装形状：	RECTANGULAR	封装形式：	IN-LINE
电源：	5 V	最大电源电流（ICC）：	17 mA
认证状态：	Not Qualified	子类别：	FF/Latches
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	TTL	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
触发器类型：	MASTER-SLAVE	Base Number Matches：	1

DM7476J 数据手册

June 1989

5476/DM5476/DM7476

Dual Master-Slave J-K Flip-Flops with Clear,

Preset, and Complementary Outputs

General Description

This device contains two independent positive pulse trig-

gered J-K flip-flops with complementary outputs. The J and

K data is processed by the flip-flop after a complete clock

pulse. While the clock is low the slave is isolated from the

master. On the positive transition of the clock, the data from

the J and K inputs is transferred to the master. While the

clock is high the J and K inputs are disabled. On the nega-

tive transition of the clock, the data from the master is trans-

ferred to the slave. The logic state of J and K inputs must

not be allowed to change while the clock is high. The data is

transfered to the outputs on the falling edge of the clock

pulse. A low logic level on the preset or clear inputs will set

or reset the outputs regardless of the logic levels of the

other inputs.

Features

Alternate Military/Aerospace device (5476) is available.

Contact a National Semiconductor Sales Office/Distrib-

utor for specifications.

Connection Diagram

Function Table

Dual-In-Line Package

Inputs

CLK

Outputs

CLR

Toggle

High Logic Level

Low Logic Level

Either Low or High Logic Level

Positive pulse data. The J and K inputs must be held constant while

the clock is high. Data is transfered to the outputs on the falling edge of the

clock pulse.

and/or clear inputs return to their inactive (high) level.

This configuration is nonstable; that is, it will not persist when the preset

TL/F/6528–1

Order Number 5476DMQB, 5476FMQB,

DM5476J, DM5476W or DM7476N

tablished.

The output logic level before the indicated input conditions were es-

See NS Package Number J16A, N16E or W16A

each complete active high level clock pulse.

Toggle

Each output changes to the complement of its previous level on

1995 National Semiconductor Corporation

TL/F/6528

RRD-B30M105/Printed in U. S. A.

12 3 4

中文翻译

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与DM7476J相关器件

型号	品牌	获取价格	描述	数据表
DM7476J/A+	ETC	获取价格	J-K-Type Flip-Flop
DM7476N	FAIRCHILD	获取价格	Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs
DM7476N	NSC	获取价格	Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs
DM7476N/A+	ETC	获取价格	J-K-Type Flip-Flop
DM7476N/B+	ETC	获取价格	J-K-Type Flip-Flop
DM7476W	NSC	获取价格	Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs
DM7483J	NSC	获取价格	IC,BINARY ADDER,STD-TTL,DIP,16PIN,CERAMIC
DM7483J/A+	ETC	获取价格	Binary Adder
DM7483N	NSC	获取价格	IC,BINARY ADDER,STD-TTL,DIP,16PIN,PLASTIC
DM7483N/A+	NSC	获取价格	IC,BINARY ADDER,STD-TTL,DIP,16PIN,PLASTIC

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