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DM54LS491J PDF预览

DM54LS491J

更新时间: 2024-11-22 22:56:47
品牌 Logo 应用领域
美国国家半导体 - NSC 计数器触发器逻辑集成电路
页数 文件大小 规格书
4页 130K
描述
10-Bit Counter

DM54LS491J 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP24,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.92
其他特性:6 MIDDLE BITS CAN BE SET H/L AS A GROUP计数方向:BIDIRECTIONAL
系列:LSJESD-30 代码:R-GDIP-T24
JESD-609代码:e0负载/预设输入:YES
逻辑集成电路类型:BINARY COUNTER最大频率@ Nom-Sup:10500000 Hz
最大I(ol):0.012 A工作模式:SYNCHRONOUS
位数:10功能数量:1
端子数量:24最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP24,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):180 mA
传播延迟(tpd):35 ns认证状态:Not Qualified
座面最大高度:5.715 mm子类别:Counters
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:10.5 MHz
Base Number Matches:1

DM54LS491J 数据手册

 浏览型号DM54LS491J的Datasheet PDF文件第2页浏览型号DM54LS491J的Datasheet PDF文件第3页浏览型号DM54LS491J的Datasheet PDF文件第4页 
July 1989  
DM54LS491/74LS491 10-Bit Counter  
General Description  
Features/Benefits  
Y
Y
Y
Y
Y
CRT vertical and horizontal timing generation  
The ten-bit counter can count up, count down, set, and load  
2 LSB’s, 2 MSB’s and 6 middle bits high or low as a group.  
All operations are synchronous with the clock. SET over-  
rides LOAD, COUNT and HOLD. LOAD overrides COUNT.  
Bus-structured pinout  
24-pin SKINNYDIP saves space  
TRI-STATE outputs drive bus lines  
É
Low current PNP inputs reduce loading  
COUNT is conditional on C , otherwise it holds.  
IN  
All outputs are enabled when OE is low, otherwise HIGH-Z.  
The 24 mA I outputs are suitable for driving RAM/PROM  
OL  
address lines in video graphics systems.  
Connection Diagram  
Standard Test Load  
Top View  
TL/L/8332–2  
TL/L/8332–1  
Order Number DM54LS491J,  
DM74LS491J or DM74LS491N  
See NS Package Number J24F or N24C  
Function Table  
OE CK SET LD CNT C UP D9-D0 Q9-Q0 Operation  
IN  
H
L
L
L
L
L
L
X
X
H
L
L
L
L
L
X
X
L
X
X
X
H
L
X
X
X
X
H
L
X
X
X
X
X
L
X
X
D
X
X
X
X
Z
H
D
Q
Q
Hi-Z  
Set all HIGH  
LOAD D  
HOLD  
u
u
u
u
u
u
H
H
H
H
HOLD  
L
Q plus 1 Count UP  
Q minus 1 Count DN  
L
L
H
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.  
C
1995 National Semiconductor Corporation  
TL/L/8332  
RRD-B30M115/Printed in U. S. A.  

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