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DM54LS502J PDF预览

DM54LS502J

更新时间: 2024-11-22 22:56:47
品牌 Logo 应用领域
美国国家半导体 - NSC 移位寄存器触发器逻辑集成电路
页数 文件大小 规格书
6页 135K
描述
8-Bit Successive Approximation Register

DM54LS502J 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.92
计数方向:RIGHT系列:LS
JESD-30 代码:R-GDIP-T16JESD-609代码:e0
长度:19.43 mm逻辑集成电路类型:SERIAL IN PARALLEL OUT
最大频率@ Nom-Sup:15000000 Hz位数:8
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
传播延迟(tpd):35 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Shift Registers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:25 MHz
Base Number Matches:1

DM54LS502J 数据手册

 浏览型号DM54LS502J的Datasheet PDF文件第2页浏览型号DM54LS502J的Datasheet PDF文件第3页浏览型号DM54LS502J的Datasheet PDF文件第4页浏览型号DM54LS502J的Datasheet PDF文件第5页浏览型号DM54LS502J的Datasheet PDF文件第6页 
April 1992  
DM54LS502/DM74LS502  
8-Bit Successive Approximation Register  
General Description  
The LS502 is an 8-bit register with the interstage logic nec-  
essary to perform serial-to-parallel conversion and provide  
an active LOW Conversion Complete (CC) signal coincident  
with storage of the eighth bit. An active LOW Start (S) input  
performs synchronous initialization which forces Q7 LOW  
and all other outputs HIGH. Subsequent clocks shift this Q7  
LOW signal downstream which simultaneously backfills the  
register such that the first serial data (D input) bit is stored in  
Q7, the second bit in Q6, the third in Q5, etc. The serial  
input data is also synchronized by an auxiliary flip-flop and  
Designed primarily for use in the successive approximation  
technique for analog-to-digital conversion, the LS502 can  
also be used as a serial-to-parallel converter ring counter  
and as the storage and control element in recursive digital  
routines.  
Features  
Y
Low power Schottky version of 2502  
Y
Storage and control for successive approximation A to  
D conversion  
brought out on Q  
.
D
Y
Performs serial-to-parallel conversion  
Connection Diagram  
Logic Symbol  
Dual-In-Line Package  
TL/F/10189–2  
e
e
V
CC  
GND  
Pin 16  
Pin 8  
TL/F/10189–1  
Order Number DM54LS502J, DM54LS502W,  
DM74LS502WM or DM74LS502N  
See NS Package Number J16A, M16B, N16E or W16A  
Pin  
Description  
Names  
D
Serial Data Input  
Start Input (Active LOW)  
S
CP  
Clock Pulse Input (Active Rising Edge)  
Synchronized Serial Data Output  
Q
D
CC  
Conversion Complete Output (Active LOW)  
Parallel Register Outputs  
Q0Q7  
Q7  
Complement of Q7 Output  
C
1995 National Semiconductor Corporation  
TL/F/10189  
RRD-B30M105/Printed in U. S. A.  

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