Datasheet > 逻辑 > 计数器> DM54LS161AW

DM54LS161AW

更新时间： 2024-11-19 22:56:47

品牌	Logo	应用领域
美国国家半导体 - NSC		计数器触发器逻辑集成电路输出元件
页数	文件大小	规格书
12页	213K
描述
Synchronous 4-Bit Binary Counters

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DM54LS161AW 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DFP, FL16,.3	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.82
Is Samacsys：	N	其他特性：	TCO OUTPUT
计数方向：	UP	系列：	LS
JESD-30 代码：	R-GDFP-F16	JESD-609代码：	e0
长度：	9.6645 mm	负载电容（CL）：	50 pF
负载/预设输入：	YES	逻辑集成电路类型：	BINARY COUNTER
最大频率@ Nom-Sup：	20000000 Hz	最大I（ol）：	0.004 A
工作模式：	SYNCHRONOUS	位数：	4
功能数量：	1	端子数量：	16
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC, GLASS-SEALED	封装代码：	DFP
封装等效代码：	FL16,.3	封装形状：	RECTANGULAR
封装形式：	FLATPACK	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V	最大电源电流（ICC）：	32 mA
传播延迟（tpd）：	38 ns	认证状态：	Not Qualified
座面最大高度：	2.032 mm	子类别：	Counters
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	TTL	温度等级：	MILITARY
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	FLAT
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	触发器类型：	POSITIVE EDGE
宽度：	6.604 mm	最小 fmax：	20 MHz
Base Number Matches：	1

DM54LS161AW 数据手册

May 1992

54LS161A/DM54LS161A/DM74LS161A,

54LS163A/DM54LS163A/DM74LS163A

Synchronous 4-Bit Binary Counters

General Description

These synchronous, presettable counters feature an inter-

nal carry look-ahead for application in high-speed counting

designs. The LS161A and LS163A are 4-bit binary counters.

The carry output is decoded by means of a NOR gate, thus

preventing spikes during the normal counting mode of oper-

ation. Synchronous operation is provided by having all flip-

flops clocked simultaneously so that the outputs change co-

incident with each other when so instructed by the count-

enable inputs and internal gating. This mode of operation

eliminates the output counting spikes which are normally

associated with asynchronous (ripple clock) counters. A

buffered clock input triggers the four flip-flops on the rising

(positive-going) edge of the clock input waveform.

gating. Instrumental in accomplishing this function are two

count-enable inputs and a ripple carry output.

Both count-enable inputs (P and T) must be high to count,

and input T is fed forward to enable the ripple carry output.

The ripple carry output thus enabled will produce a high-lev-

el output pulse with a duration approximately equal to the

high-level portion of the Q output. This high-level overflow

ripple carry pulse can be used to enable successive cascad-

ed stages. High-to-low level transitions at the enable P or T

inputs may occur, regardless of the logic level of the clock.

These counters feature a fully independent clock circuit.

Changes made to control inputs (enable P or T or load) that

will modify the operating mode have no effect until clocking

occurs. The function of the counter (whether enabled, dis-

abled, loading, or counting) will be dictated solely by the

conditions meeting the stable set-up and hold times.

These counters are fully programmable; that is, the outputs

may be preset to either level. As presetting is synchronous,

setting up a low level at the load input disables the counter

and causes the outputs to agree with the setup data after

the next clock pulse, regardless of the levels of the enable

input. The clear function for the LS161A is asynchronous;

and a low level at the clear input sets all four of the flip-flop

outputs low, regardless of the levels of clock, load, or en-

able inputs. The clear function for the LS163A is synchro-

nous; and a low level at the clear inputs sets all four of the

flip-flop outputs low after the next clock pulse, regardless of

the levels of the enable inputs. This synchronous clear al-

lows the count length to be modified easily, as decoding the

maximum count desired can be accomplished with one ex-

ternal NAND gate. The gate output is connected to the clear

input to synchronously clear the counter to all low outputs.

Features

Synchronously programmable

Internal look-ahead for fast counting

Carry output for n-bit cascading

Synchronous counting

Load control line

Diode-clamped inputs

Typical propagation time, clock to Q output 14 ns

Typical clock frequency 32 MHz

Typical power dissipation 93 mW

Alternate

Military/Aerospace

device

(54LS161,

The carry look-ahead circuitry provides for cascading coun-

ters for n-bit synchronous applications without additional

54LS163) is available. Contact a National Semiconduc-

tor Sales Office/Distributor for specificaitons.

Connection Diagram

Dual-In-Line Package

Order Numbers 54LS161ADMQB, 54LS161AFMQB,

54LS161ALMQB, 54LS163ADMQB, 54LS163AFMQB,

54LS163ALMQB, DM54LS161AJ, DM54LS161AW,

DM54LS163AJ, DM54LS163AW, DM74LS161AM,

DM74LS161AN, DM74LS163AM or DM74LS163AN

See NS Package Number E20A, J16A,

M16A, N16E or W16A

TL/F/6397–1

1995 National Semiconductor Corporation

TL/F/6397

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6 7...12

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与DM54LS161AW相关器件

型号	品牌	获取价格	描述	数据表
DM54LS161AW/883	TI	获取价格	LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDFP16, CERAMIC, DFP-16
DM54LS161AW/883B	NSC	获取价格	IC,COUNTER,UP,4-BIT BINARY,LS-TTL,FP,16PIN,CERAMIC
DM54LS161AW/883C	NSC	获取价格	IC,COUNTER,UP,4-BIT BINARY,LS-TTL,FP,16PIN,CERAMIC
DM54LS161J/883	ETC	获取价格	Synchronous Up Counter
DM54LS161J/883B	NSC	获取价格	IC,COUNTER,UP,4-BIT BINARY,LS-TTL,DIP,16PIN,CERAMIC
DM54LS161W/883	ETC	获取价格	Synchronous Up Counter
DM54LS161W/883B	NSC	获取价格	IC,COUNTER,UP,4-BIT BINARY,LS-TTL,FP,16PIN,CERAMIC
DM54LS161W/883C	NSC	获取价格	IC,COUNTER,UP,4-BIT BINARY,LS-TTL,FP,16PIN,CERAMIC
DM54LS163A	NSC	获取价格	Synchronous 4-Bit Binary Counters
DM54LS163AE	NSC	获取价格	Synchronous 4-Bit Binary Counters

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