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DM54LS154W-MLS PDF预览

DM54LS154W-MLS

更新时间: 2024-11-08 20:48:39
品牌 Logo 应用领域
美国国家半导体 - NSC 驱动输出元件逻辑集成电路
页数 文件大小 规格书
6页 124K
描述
IC LS SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, CDFP24, CERPACK-24, Decoder/Driver

DM54LS154W-MLS 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DFP, FL24,.4Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.61系列:LS
JESD-30 代码:R-GDFP-F24JESD-609代码:e0
长度:15.113 mm逻辑集成电路类型:OTHER DECODER/DRIVER
最大I(ol):0.004 A功能数量:1
端子数量:24最高工作温度:125 °C
最低工作温度:-55 °C输出极性:INVERTED
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装等效代码:FL24,.4封装形状:RECTANGULAR
封装形式:FLATPACK包装方法:RAIL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):14 mAProp。Delay @ Nom-Sup:35 ns
传播延迟(tpd):35 ns认证状态:Not Qualified
筛选级别:38535Q/M;38534H;883B座面最大高度:2.54 mm
子类别:Decoder/Drivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

DM54LS154W-MLS 数据手册

 浏览型号DM54LS154W-MLS的Datasheet PDF文件第2页浏览型号DM54LS154W-MLS的Datasheet PDF文件第3页浏览型号DM54LS154W-MLS的Datasheet PDF文件第4页浏览型号DM54LS154W-MLS的Datasheet PDF文件第5页浏览型号DM54LS154W-MLS的Datasheet PDF文件第6页 
May 1989  
DM54LS154/DM74LS154 4-Line to 16-Line  
Decoders/Demultiplexers  
General Description  
Features  
Y
Decodes 4 binary-coded inputs into one of 16 mutually  
exclusive outputs  
Each of these 4-line-to-16-line decoders utilizes TTL circuit-  
ry to decode four binary-coded inputs into one of sixteen  
mutually exclusive outputs when both the strobe inputs, G1  
and G2, are low. The demultiplexing function is performed  
by using the 4 input lines to address the output line, passing  
data from one of the strobe inputs with the other strobe  
input low. When either strobe input is high, all outputs are  
high. These demultiplexers are ideally suited for implement-  
ing high-performance memory decoders. All inputs are buff-  
ered and input clamping diodes are provided to minimize  
transmission-line effects and thereby simplify system de-  
sign.  
Y
Performs the demultiplexing function by distributing data  
from one input line to any one of 16 outputs  
Input clamping diodes simplify system design  
High fan-out, low-impedance, totem-pole outputs  
Typical propagation delay  
Y
Y
Y
3 levels of logic 23 ns  
Strobe 19 ns  
Y
Typical power dissipation 45 mW  
Connection and Logic Diagrams  
Dual-In-Line Package  
TL/F/6394–1  
Order Number DM54LS154J,  
DM74LS154WM or DM74LS154N  
See NS Package Number J24A, M24B or N24A  
TL/F/6394–2  
C
1995 National Semiconductor Corporation  
TL/F/6394  
RRD-B30M105/Printed in U. S. A.  

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