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DM5438W PDF预览

DM5438W

更新时间: 2024-11-23 23:47:19
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其他 - ETC 触发器逻辑集成电路
页数 文件大小 规格书
4页 108K
描述
Quad 2-input NAND Gate

DM5438W 数据手册

 浏览型号DM5438W的Datasheet PDF文件第2页浏览型号DM5438W的Datasheet PDF文件第3页浏览型号DM5438W的Datasheet PDF文件第4页 
June 1989  
DM5438/DM7438 Quad 2-Input NAND Buffers  
with Open-Collector Outputs  
General Description  
Pull-Up Resistor Equations  
b
This device contains four independent gates each of which  
performs the logic NAND function. The open-collector out-  
puts require external pull-up resistors for proper logical op-  
eration.  
V
CC  
(Min)  
V
OH  
e
R
MAX  
a
N
1
(I  
OH  
)
N
2
(I  
IH  
)
b
V
OL  
V
(Max)  
CC  
e
R
MIN  
b
I
N
(I )  
OL  
3
IL  
total maximum output high current for all  
e
outputs tied to pull-up resistor  
Where: N (I  
1
)
OH  
e
)
IH  
N
(I  
total maximum input high current for all  
2
inputs tied to pull-up resistor  
e
inputs tied to pull-up resistor  
N
(I  
IL  
)
total maximum input low current for all  
3
Connection Diagram  
Dual-In-Line Package  
TL/F/6513–1  
Order Number DM5438J, DM5438W, DM7438M or DM7438N  
See NS Package Number J14A, M14A, N14A or W14B  
Function Table  
e
Y
AB  
Inputs  
Output  
Y
A
B
L
L
L
H
L
H
H
H
L
H
H
H
e
e
H
L
High Logic Level  
Low Logic Level  
C
1995 National Semiconductor Corporation  
TL/F/6513  
RRD-B30M105/Printed in U. S. A.  

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