Datasheet > DM4M32SJ-12

DM4M32SJ-12

更新时间： 2024-02-26 22:56:10

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
24页	165K
描述
Enhanced DRAM (EDRAM) Module

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中文翻译

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技术参数
数据手册

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DM4M32SJ-12 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	SIMM
包装说明：	SIMM, SSIM72	针数：	72
Reach Compliance Code：	unknown	风险等级：	5.92
Is Samacsys：	N	最长访问时间：	12 ns
I/O 类型：	COMMON	JESD-30 代码：	R-PSMA-N72
内存密度：	134217728 bit	内存集成电路类型：	CACHE DRAM MODULE
内存宽度：	32	端子数量：	72
字数：	4194304 words	字数代码：	4000000
最高工作温度：	70 °C	最低工作温度：
组织：	4MX32	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SIMM
封装等效代码：	SSIM72	封装形状：	RECTANGULAR
封装形式：	MICROELECTRONIC ASSEMBLY	峰值回流温度（摄氏度）：	240
电源：	5 V	认证状态：	Not Qualified
刷新周期：	1024	座面最大高度：	35.56 mm
自我刷新：	YES	最大待机电流：	0.036 A
子类别：	DRAMs	最大压摆率：	7.52 mA
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	NO LEAD	端子节距：	1.27 mm
端子位置：	SINGLE	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

DM4M32SJ-12 数据手册

DM4M32SJ

4Mb x 32 Enhanced DRAM SIM

Enhanced

Memory Systems Inc.

Product Specification

Features

Architecture

The DM4M32SJ achieves

4Mb x 32 density by mounting

32 4M x 1 EDRAMs, packaged

in 28-pin plastic SOJ packages

on both sides of the multi-

layer substrate. Four buffers

have been added to reduce the

loading on the address and

control lines. The buffers have

■ Integrated 2,048 x 32 SRAM Cache Row Register Allows 12ns

Access Random Reads Within the Page

■ Interleaved SRAM Cache for 8ns Burst Reads

■ 30ns DRAM Array for Fast Random Access to Any Page

■ Ultra-Fast Integrated 8Kbyte-Wide DRAM to Cache Bus

for 454-Gbyte/sec Cache Fill Bandwidth

■ On-Chip Write Posting and Fast Page Mode Operation Allows

12ns Writes and Burst Writes

■ On-Board Address and Control Buffering

■ Low Power Self Refresh Mode Option

balanced output current levels

and current limiting resistors.

These offer low ground

bounce, minimal undershoot,

and controlled fall times.

Description

The Enhanced Memory Systems 16MB EDRAM SIMM module

provides a single memory module solution for the main memory or

local memory of fast PCs, workstations, servers, and other high

performance systems. Due to its fast 12ns cache row register, the

EDRAM memory module supports zero-wait-state burst read

operations at up to 66MHz bus rates in a non-interleave configuration

and >100MHz bus rates with a two-way interleave configuration.

On-chip write posting and fast page mode operation supports

12ns write and burst write operations. On a cache miss, the fast

DRAM array reloads the entire 8Kbyte cache over an 8Kbyte-wide bus

in 18ns for an effective bandwidth of 454 Gbytes/sec. This means very

low latency and fewer wait states on a cache miss than a non-

integrated cache/DRAM solution. The JEDEC compatible SIMM

configuration allows a single memory controller to be designed to

support either JEDEC slow DRAMs or high speed EDRAMs to provide

a simple upgrade path to higher system performance.

The EDRAM memory

module architecture is very

similar to a standard 16MB DRAM module with the addition of an

integrated cache and on-chip control which allows it to operate much

like a page mode or static column DRAM.

The EDRAM's SRAM cache is integrated into the DRAM array as

tightly coupled row registers. Memory reads always occur from the

cache row register. When the on-chip comparator detects a page hit,

only the SRAM is accessed and data is available in 12ns from column

address. When a page read miss is detected, the entire new DRAM row

is updated into the cache and data is available at the output all within

a single 30ns access. Subsequent reads within the page (burst reads,

local instructions, or data) will continue at 12ns cycle time. Since reads

occur from the SRAM cache, DRAM precharge can occur simultaneously

without degrading performance. The on-chip refresh counter with

independent refresh bus allows the EDRAM to

be refreshed during cache reads.

DM4M32SJ Functional Diagram

Memory writes are internally posted in

12ns and directed to the DRAM array. During

a write hit, the on-chip address comparator

activates a parallel write path to the SRAM

cache to maintain coherency. The EDRAM

delivers 12ns cycle page mode memory writes.

Memory writes do not affect the contents of

0-10

Column

Add

Latch

CAL

0-3

Column Decoder

2048 X 32 Cache (Row Register)

11-Bit

Comp

Sense Amps

& Column Write Select

I/O

Control

and

Data

Latches

Last

Row

Read

Add

0-31

0-10

the cache row register except during a cache

hit.

Latch

By integrating the SRAM cache as row

registers in the DRAM array and keeping the

on-chip control simple, the EDRAM is able to

provide superior performance over standard

slow DRAMs.

Memory

Array

16Mbyte

Row

Add

Latch

0-9

1-36

Row Add

and

Refresh

Control

Refresh

Counter

W/R

0,2

PD16M

Telephone (800) 545-DRAM; Fax (719) 488-9095; http://www.csn.net/ramtron/enhanced

The information contained herein is subject to change without notice. Enhanced reserves the right

to change or discontinue this product without notice.

38-2110-002

12 3 4 5 6 7...24

中文翻译

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与DM4M32SJ-12相关器件

型号	品牌	获取价格	描述	数据表
DM4M32SJ-12L	ETC	获取价格	Enhanced DRAM (EDRAM) Module
DM4M32SJ-15	ETC	获取价格	Enhanced DRAM (EDRAM) Module
DM4M32SJ-15L	ETC	获取价格	Enhanced DRAM (EDRAM) Module
DM4M32SJ-20	RAMTRON	获取价格	Cache DRAM Module, 4MX32, 20ns, CMOS, SIMM-72
DM4M32SJ6-10	ETC	获取价格	Enhanced DRAM (EDRAM) Module
DM4M32SJ6-12	ETC	获取价格	Enhanced DRAM (EDRAM) Module
DM4M32SJ6-12L	ETC	获取价格	Enhanced DRAM (EDRAM) Module
DM4M32SJ6-15	ETC	获取价格	Enhanced DRAM (EDRAM) Module
DM4M32SJ6-15L	ETC	获取价格	Enhanced DRAM (EDRAM) Module
DM4M36SJ-15	RAMTRON	获取价格	Cache DRAM Module, 4MX36, 15ns, CMOS, SIMM-72

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