Datasheet > DM2M32SJ6-15I

DM2M32SJ6-15I

更新时间： 2024-11-09 20:20:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		动态存储器内存集成电路
页数	文件大小	规格书
20页	148K
描述
EDO DRAM Module, 2MX32, 15ns, CMOS, PSMA72,

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

DM2M32SJ6-15I 技术参数

是否Rohs认证：	不符合	生命周期：	Active
包装说明：	SIMM, SSIM72	Reach Compliance Code：	compliant
风险等级：	5.83	最长访问时间：	15 ns
I/O 类型：	COMMON	JESD-30 代码：	R-PSMA-N72
内存密度：	67108864 bit	内存集成电路类型：	EDO DRAM MODULE
内存宽度：	32	端子数量：	72
字数：	2097152 words	字数代码：	2000000
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	2MX32	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SIMM
封装等效代码：	SSIM72	封装形状：	RECTANGULAR
封装形式：	MICROELECTRONIC ASSEMBLY	电源：	5 V
认证状态：	Not Qualified	刷新周期：	1024
座面最大高度：	24.257 mm	自我刷新：	NO
最大待机电流：	0.016 A	子类别：	DRAMs
最大压摆率：	1.44 mA	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	NO LEAD
端子节距：	1.27 mm	端子位置：	SINGLE
Base Number Matches：	1

DM2M32SJ6-15I 数据手册

DM2M36SJ6/DM2M32SJ6 Multibank EDO

2Mbx36/2Mbx32 Enhanced DRAM SIMM

Product Specification

Enhanced

Memory Systems Inc.

Features

Architecture

The DM2M36SJ6 achieves

2Mb x 36 density by mounting

18 1Mb x 4 EDRAMs, packaged

in 28-pin plastic SOJ packages,

on both sides of the multi-layer

substrate. Sixteen DM2242 and

two DM2252 devices provide

data and parity storage. The

DM2M32SJ6 contains 16

DM2242 devices for data only.

The EDRAM memory

module architecture is very

similar to a standard 8MB

DRAM module with the addition

of an integrated cache and on-

■ 16KByte SRAM Cache Memory for 12ns Random Reads Within Eight

Active Pages (Multibank Cache)

■ Fast DRAM Array for 30ns Access to Any New Page

■ Write Posting Register for 12ns Random Writes and Burst Writes

Within a Page (Hit or Miss)

■ 2KByte Wide DRAM to SRAM Bus for 113.6 Gigabytes/Sec Cache Fill

■

On-chip Cache Hit/Miss Comparators Maintain Cache Coherency on Writes

■ Hidden Precharge and Refresh Cycles

■ Extended 64ms Refresh Period for Low Standby Power

■

Standard CMOS/TTL Compatible I/O Levels and +5 or 3.3V Volt Supply

■ Compatibility with JEDEC 2M x 36 DRAM SIMM Configuration

Allows Performance Upgrade in System

■

Multibank Extended Data Output (EDO) for Faster System Operation

■ Low Power, Self Refresh Option

■ Industrial Temperature Range Option

chip control which allows it to

Description

operate much like an EDO DRAM.

The Enhanced Memory Systems Multibank EDO 8MB EDRAM

SIMM module provides a single memory module solution for the main

memory or local memory of fast PCs, workstations, servers, and other

high performance systems. Due to its fast 12ns cache row register,

the EDRAM memory module supports zero-wait-state burst read

operations at up to 83MHz bus rates in a non-interleave configuration

and >132MHz bus rates with a two-way interleave configuration.

On-chip write posting and fast page mode operation supports

12ns write and burst write operations. On a cache miss, the fast

DRAM array reloads the 2KByte cache over a 2KByte-wide bus in

18ns for an effective bandwidth of 113.6 Gbytes/sec. This means

very low latency and fewer wait states on a cache miss than a non-

integrated cache/DRAM solution. The JEDEC compatible 72-bit

SIMM configuration allows a single memory controller to be designed to

support either JEDEC slow DRAMs or high speed EDRAMs to provide a

simple upgrade path to higher system performance.

The EDRAM’s SRAM cache is integrated into the DRAM array as

tightly coupled row registers. Each EDRAM Bank has a total of four

independent DRAM memory banks each with its own SRAM row

one of these banks as specified by row address bits A and A (bank

select). When the internal comparator detects that the row address

matches the last row read from any of the four DRAM banks (page

hit), the SRAM is accessed and data is available on the output pins in

12ns from the column address input. Subsequent reads within the

page (burst reads or random reads) can continue at 12ns cycle

time. When the row address does not match the last row read from

any of the last four DRAM banks (page miss), the new DRAM row is

accessed and loaded into the appropriate SRAM row register and

data is available on the output pins all within 30ns from row enable.

Subsequent reads within the page (burst reads or random reads)

can continue at 12ns cycle time.

Functional Diagram

Since reads occur from the SRAM

cache, the DRAM precharge can occur

during burst reads. This eliminates the

precharge time delay suffered by other

DRAMs and SDRAMs when accessing a

0-8

Column

Add

Latch

/CAL

0-3,P

Column Decoder

4 - 512 x 36 Cache Pages

(Row Registers) x 2

8-Bit

Comp

new page. The EDRAM has an

independent on-chip refresh counter and

dedicated refresh control pin to allow the

Sense Amps

& Column Write Select

I/O

Control

and

Data

Latches

8 Last

Row

Read

Add

0-10

0-35

DRAM array to be refreshed concurrently

with cache read operations (hidden

refresh).

Memory writes are posted to the

input data latch and directed to the DRAM

array. During a write hit, the on-chip

address comparator activates a parallel

write path to the SRAM cache to maintain

Latch

0, 1

Memory

Array

2048 x 512 x 36 x 2

Row

Add

Latch

/WE

0-9

1-18

Row Add

and

Refresh

Control

Refresh

Counter

W/R

/RE

0,2,3

Telephone (800) 545-DRAM; Fax (719) 488-9095; http://www.csn.net/ramtron/enhanced

80921

38-2119-000

The information contained herein is subject to change without notice.

Enhanced reserves the right to change or discontinue this product without notice.

12 3 4 5 6 7...20

中文翻译

下载PDF

与DM2M32SJ6-15I相关器件

型号	品牌	获取价格	描述	数据表
DM2M32SJ6-15L	RAMTRON	获取价格	EDO DRAM Module, 2MX32, 15ns, CMOS, PSMA72
DM2M32SJ6-15L	CYPRESS	获取价格	EDO DRAM Module, 2MX32, 15ns, CMOS, PSMA72,
DM2M32SJ7-12	CYPRESS	获取价格	EDO DRAM Module, 2MX32, 12ns, CMOS, PSMA72,
DM2M32SJ7-12I	RAMTRON	获取价格	EDO DRAM Module, 2MX32, 12ns, CMOS, PSMA72
DM2M32SJ7-12I	CYPRESS	获取价格	EDO DRAM Module, 2MX32, 12ns, CMOS, PSMA72,
DM2M32SJ7-12L	ETC	获取价格	Enhanced DRAM (EDRAM) Module
DM2M32SJ7-15	CYPRESS	获取价格	EDO DRAM Module, 2MX32, 15ns, CMOS, PSMA72,
DM2M32SJ7-15I	CYPRESS	获取价格	EDO DRAM Module, 2MX32, 15ns, CMOS, PSMA72,
DM2M32SJ7-15I	RAMTRON	获取价格	Cache DRAM Module, 2MX32, 35ns, MOS, SIMM-72
DM2M32SJ7-15L	ETC	获取价格	Enhanced DRAM (EDRAM) Module

与DM2M32SJ6-15I相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

22
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

21
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

47
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

39

产品中心

服务支持

精选活动

关于我们

帮助中心

DM2M32SJ6-15I

DM2M32SJ6-15I 技术参数

DM2M32SJ6-15I 数据手册

与DM2M32SJ6-15I相关器件

与DM2M32SJ6-15I相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

DM2M32SJ6-15I

DM2M32SJ6-15I 技术参数

DM2M32SJ6-15I 数据手册

与DM2M32SJ6-15I相关器件

与DM2M32SJ6-15I相关文章

您还可以找

您在本页遇到什么问题？