cache reads concurrently with precharge. During write sequences, the output pin Q (as shown below). The specific databit selected to
a write operation is not performed unless both /CAL and /WE are the output is determined by column addresses A and A . System
9
10
low. As a result, the /CAL input can be used as a byte write select in operation is consistent with the standard “Functional Description”
multi-chip systems.
and timing diagrams shown in this specification. See the note in the
read timing diagrams and “Switching Characteristics” chart for the
faster access and data hold times.
DRAM Write Miss
If a DRAM write request is initiated by clocking /RE while W/R,
/CAL, /WE, and /F are high, the EDRAM will compare the new row
address to the LRR address latch (an 11-bit latch loaded on each
/RE active read miss cycle). If the row address does not match, the
EDRAM will write data to the DRAM array only and contents of the
current cache are not modified. The write address and data are
posted to the DRAM as soon as the column address is latched by
bringing /CAL low and the write data is latched by bringing /WE
low. The write address and data can be latched very quickly after
the fall of /RE (tRAH + tASC for the column address and tDS for the
data). During a write burst sequence, the second write data can be
posted at time tRSW after /RE. Subsequent writes within a page can
occur with write cycle time tPC. During a write miss sequence,
cache reads are inhibited and the output buffers are disabled
(independently of /G) until time tWRR after /RE goes high. At the
end of a write sequence (after /CAL and /WE are brought high and
tRE is satisfied), /RE can be brought high to precharge the memory.
It is possible to perform cache reads concurrently with the
precharge. During write sequences, a write operation is not
performed unless both /CAL and /WE are low. As a result, /CAL can
be used as a byte write select in multi-chip systems.
Internal Refresh
If /F is active (low) on the assertion of /RE, an internal refresh
cycle is executed. This cycle refreshes the row address supplied by
an internal refresh counter. This counter is incremented at the end
of the cycle in preparation for the next /F refresh cycle. At least
1,024 /F cycles must be executed every 64ms. /F refresh cycles can
be hidden because cache memory can be read under column
address control throughout the entire /F cycle.
DM2200 Datapath Architecture
EDRAM
Row Address
4M DRAM Array
A
0-10
2,048 Bits
EDRAM
2K SRAM Cache
Column Address
A
2-10
128 Bits
Column Address
4 to 1
Output Selector
/RE Inactive Operation
A A
9, 10
It is possible to read data from the SRAM cache without
clocking /RE. This option is desirable when the external control
logic is capable of fast hit/miss comparison. In this case, the
controller can avoid the time required to perform row/column
multiplexing on hit cycles. This capability also allows the EDRAM to
perform cache read operations during precharge and refresh
cycles to minimize wait states and reduce power. It is only
necessary to select /S and /G and provide the appropriate column
address to read data as shown in the table below. The row address
of the SRAM cache accessed without clocking /RE will be specified
by the LRR address latch loaded during the last /RE active read
cycle. To perform a cache read in static column mode, /CAL is held
high, and the cache contents at the specified column address will
be valid at time tAC after address is stable. To perform a cache read
in page mode, /CAL is clocked to latch the column address. The
cache data is valid at time tAC after the column address is setup to
/CAL.
1 Bit
Q
Low Power Mode
The EDRAM enters its low power mode when /S is high. In this
mode, the internal DRAM circuitry is powered down to reduce
standby current to 1mA.
Low Power, Self-Refresh Option
When the low power, self-refresh option is specified when
ordering the EDRAM, the EDRAM enters this mode when /RE is
clocked while /S, W/R, /F, and /WE are high; and /CAL is low. In this
mode, the power is turned off to all I/O pins except /RE to
minimize chip power, and an on-board refresh clock is enabled to
perform self-refresh cycles using the on-board refresh counter. The
EDRAM remains in this low power mode until /RE is brought high
again to terminate the mode. The EDRAM /RE input must remain
high for tRP2 following exit from self-refresh mode to allow any on-
going internal refresh to terminate prior to the next memory
operation.
On-Chip SRAM Interleave
The DM2200 has an on-chip interleave of its SRAM cache
which allows 8ns random accesses (tAC1) for up to three data
words (burst reads) following an initial read access (hit or miss).
The SRAM cache is integrated into the DRAM arrays in a 512 x 4
organization. It is converted into a 2K x 1 page organization by
using an on-chip address multiplexer to select one of four bits to
+3.3 Volt Power Supply Operation
If the +3.3 volt power supply option is specified, the EDRAM
will operate from a +3.3 volt ±0.3 volt power supply and all inputs
and outputs will have LVTTL/LVCMOS compatible signal levels. The
+3.3 volt EDRAM will not accept input levels which exceed the
power supply voltage. If mixed I/O levels are expected in your
system, please specify the +5 volt version of the EDRAM.
Function
/S
L
/G /CAL
A
0-8
Cache Read (Static Column)
Cache Read (Page Mode)
L
L
H
Column Address
Column Address
↓
/CAL Before /RE Refresh (“/CAS Before /RAS”)
/CAL before /RE refresh, a special case of internal refresh, is
discussed in the “Reduced Pin Count Operation” section below.
L
H = High; L = Low; X = Don’t Care; ↓ = Transitioning
1-3
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