4 ADC/8 DAC with PLL,
192 kHz, 24-Bit Codec
AD1939
Data Sheet
FEATURES
GENERAL DESCRIPTION
PLL generated or direct master clock
Low EMI design
112 dB DAC/107 dB ADC dynamic range and SNR
−94 dB THD + N
Single 3.3 V supply
Tolerance for 5 V logic inputs
Supports 24-bits and 8 kHz to 192 kHz sample rates
Differential ADC input
Differential DAC output
Log volume control with autoramp function
SPI controllable for flexibility
Software-controllable clickless mute
Software power-down
The AD1939 is a high performance, single-chip codec that
provides four analog-to-digital converters (ADCs) with
differential input, and eight digital-to-analog converters (DACs)
with differential output using the Analog Devices, Inc. patented
multibit sigma-delta (Σ-Δ) architecture. An SPI port is included,
allowing a microcontroller to adjust volume and many other
parameters. The AD1939 operates from 3.3 V digital and analog
supplies. The AD1939 is available in a 64-lead (differential
output) LQFP package.
The AD1939 is designed for low EMI. This consideration is
apparent in both the system and circuit design architectures.
By using the on-board PLL to derive the master clock from the
LR clock or from an external crystal, the AD1939 eliminates
the need for a separate high frequency master clock and can
also be used with a suppressed bit clock. The DACs and ADCs
are designed using the latest Analog Devices continuous time
architectures to further minimize EMI. By using 3.3 V supplies,
power consumption is minimized, further reducing emissions.
Right-justified, left-justified, I2S, and TDM modes
Master and slave modes up to 16-channel input/output
64-lead LQFP package
Qualified for automotive applications
APPLICATIONS
Automotive audio systems
Home Theater Systems
Set-top boxes
Digital audio effects processors
FUNCTIONAL BLOCK DIAGRAM
DIGITAL AUDIO
INPUT/OUTPUT
AD1939
SERIAL DATA PORT
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
SDATA
OUT
SDATA
IN
ADC
ADC
ADC
ADC
DIGITAL
FILTER
AND
VOLUME
CONTROL
ANALOG
AUDIO
INPUTS
CLOCKS
ANALOG
AUDIO
OUTPUTS
DIGITAL
FILTER
TIMING MANAGEMENT
AND CONTROL
(CLOCK AND PLL)
SPI
PRECISION
VOLTAGE
REFERENCE
CONTROL PORT
CONTROL DATA
INPUT/OUTPUT
Figure 1.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2006–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com