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DLPR100DWC PDF预览

DLPR100DWC

更新时间: 2024-11-30 12:44:51
品牌 Logo 应用领域
德州仪器 - TI PC可编程只读存储器
页数 文件大小 规格书
15页 234K
描述
DLP® Configuration PROM for DLPC100

DLPR100DWC 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantHTS代码:8542.32.00.71
风险等级:5.81Samacsys Description:DLP? Configuration PROM for DLPC100
JESD-30 代码:R-PDSO-G8内存密度:16777216 bit
内存集成电路类型:MEMORY CIRCUIT内存宽度:8
湿度敏感等级:3端子数量:8
字数:2097152 words字数代码:2000000
最高工作温度:85 °C最低工作温度:-40 °C
组织:2MX8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:2.5/3.3 V
认证状态:Not Qualified最大待机电流:0.00005 A
子类别:OTP ROMs表面贴装:YES
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED

DLPR100DWC 数据手册

 浏览型号DLPR100DWC的Datasheet PDF文件第2页浏览型号DLPR100DWC的Datasheet PDF文件第3页浏览型号DLPR100DWC的Datasheet PDF文件第4页浏览型号DLPR100DWC的Datasheet PDF文件第5页浏览型号DLPR100DWC的Datasheet PDF文件第6页浏览型号DLPR100DWC的Datasheet PDF文件第7页 
DLPR100  
www.ti.com  
DLPS020 DECEMBER 2009  
®
DLP Configuration PROM for DLPC100  
Check for Samples: DLPR100  
1
FEATURES  
Programmed for Use With the DLPC100 and DLP1700 (0.17 HVGA Chipset)  
Data Transfer up to 150 M-Bits/Second  
Single 2.7 to 3.6 V Supply  
5 mA Active-Current, 1-μA Powerdown (Typ)  
–40°C to 85°C Operating Temperature Range  
DESCRIPTION  
The DLPR100 is one of three components in the 0.17 HVGA chipset (see Block Diagram). Proper function and  
operation of the DLPR100 requires that it be used in conjunction with the other components of the 0.17 HVGA  
chipset. Refer to the 0.17 HVGA Chip-Set data sheet for further details (TI Literature Number DLPS017).  
The serial flash device provides a storage solution for the DLPC100 device in the 0.17 HVGA chipset. The  
device operates on a single 2.7 V to 3.6 V power supply with current consumption as low as 5 mA active and 1  
µA for power-down. The DLPR100 supports the standard Serial Peripheral Interface (SPI). SPI clock frequencies  
of up to 75 MHz are supported.  
ORDERING INFORMATION  
TA  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
–40°C to 85°C  
DLPR100DWC  
By Pin 1  
V
1
2
3
4
8
7
6
5
CS  
DO  
CC  
HOLD  
CLK  
WP  
GND  
DIO  
TERMINAL FUNCTIONS  
TERMINAL  
NAME  
I/O  
DESCRIPTION  
NO.  
1
Chip select, active low. When CS is high, the device is deselected and DO pin is high  
impedance.  
CS  
DO  
WP  
I
O
I
2
Data output. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.  
Write protect input, active low. Disables writes to the status register when the Status Register  
Protect (SRP) bit is set to a 1 state.  
3
4
5
6
GND  
DIO  
I/O  
I
Ground  
Data input/output. Data is latched on the rising edge of the CLK input pin.  
Serial clock. Provides the timing clock for the serial input and output operation.  
CLK  
Hold input, active low. Allows the device to be paused. When HOLD is brought low, while CS  
is low, the DO pin will be at high impedance and signals on the DIO and CLK pins will be  
ignored. Device operation will resume when HOLD is brought high.  
7
8
HOLD  
VCC  
I
Power supply  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009, Texas Instruments Incorporated  

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