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DG444_06

更新时间： 2024-11-20 04:14:35
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英特矽尔 - INTERSIL 开关
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12页 303K
描述
Monolithic, Quad SPST, CMOS Analog Switches

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DG444_06 数据手册

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DG444, DG445  
®
Data Sheet  
June 4, 2007  
FN3586.10  
Monolithic, Quad SPST, CMOS Analog  
Switches  
Features  
• ON Resistance (Max). . . . . . . . . . . . . . . . . . . . . . . . . 85Ω  
The DG444 and DG445 monolithic CMOS analog switches  
are drop-in replacements for the popular DG211 and DG212  
series devices. They include four independent single pole  
single throw (SPST) analog switches and TTL and CMOS  
compatible digital inputs.  
• Low Power Consumption (P ) . . . . . . . . . . . . . . . <35μW  
D
• Fast Switching Action  
- t  
- t  
(Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns  
ON  
(Max, DG444) . . . . . . . . . . . . . . . . . . . . . . . 140ns  
OFF  
• Low Charge Injection  
These switches feature lower analog ON resistance (<85Ω)  
and faster switch time (t  
and DG212. Charge injection has been reduced, simplifying  
sample and hold applications.  
<250ns) compared to the DG211  
ON  
• Upgrade from DG211, DG212  
• TTL, CMOS Compatible  
• Single or Split Supply Operation  
• Pb-Free Plus Anneal Available (RoHS Compliant)  
The improvements in the DG444 series are made possible  
by using a high voltage silicon-gate process. An epitaxial  
layer prevents the latch-up associated with older CMOS  
technologies. The 44V maximum voltage range permits  
controlling ±20V signals when operating with ±20V power  
supplies.  
Applications  
• Audio Switching  
• Battery Operated Systems  
• Data Acquisition  
The four switches are bilateral, equally matched for AC or  
bidirectional signals. The ON resistance variation with  
analog signals is quite low over a ±5V analog input range.  
The switches in the DG444 and DG445 are identical,  
differing only in the polarity of the selection logic.  
• Hi-Rel Systems  
• Sample and Hold Circuits  
• Communication Systems  
• Automatic Test Equipment  
Pinout  
DG444, DG445  
(16 LD SOIC, TSSOP)  
TOP VIEW  
Ordering Information  
PART  
PART  
TEMP.  
PKG.  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
IN  
D
IN  
D
NUMBER  
MARKING RANGE (°C) PACKAGE DWG. #  
1
1
1
2
DG444DY*  
DG444DY -40 to +85 16 Ld SOIC M16.15  
2
S
S
2
DG444DYZ* DG444DYZ -40 to +85 16 Ld SOIC M16.15  
(Note) (Pb-free)  
V-  
V+  
DG444DVZ* DG444DVZ -40 to +85 16 Ld TSSOP M16.173  
(Note)  
GND  
V
S
L
3
(Pb-free)  
S
D
4
4
4
DG445DY*  
DG445DY  
-40 to +85 16 Ld SOIC M16.15  
D
3
DG445DYZ* DG445DYZ -40 to +85 16 Ld SOIC M16.15  
(Note) (Pb-free)  
IN  
IN  
3
DG445DVZ* DG445DVZ -40 to +85 16 Ld TSSOP M16.173  
(Note)  
(Pb-free)  
*Add “-T” suffix for tape and reel.  
NOTE: Intersil Pb-free plus anneal products employ special Pb-free  
material sets; molding compounds/die attach materials and 100% matte  
tin plate termination finish, which are RoHS compliant and compatible  
with both SnPb and Pb-free soldering operations. Intersil Pb-free  
products are MSL classified at Pb-free peak reflow temperatures that  
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright © Intersil Americas Inc. 1999, 2003, 2004, 2006, 2007. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  
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