New Product
DG4051A/DG4052A/DG4053A
Vishay Siliconix
8-Channel, Dual 4-Channel, Triple 2-Channel
Multiplexers, with 0.5 pC Charge Injection
DESCRIPTION
FEATURES
The DG4051A, DG4052A and DG4053A are precision low
voltage, single and dual supply CMOS analog multiplexers.
The DG4051A is an 8-channel multiplexer, the DG4052A is
a dual 4-channel multiplexer and the DG4053A is a triple
2-channel multiplexer or triple SPDT.
They are designed to operate from a + 2.7 V to + 12 V single
supply or from 2.5 V to 5 V dual supplies and are fully
specified at + 3 V, + 5 V and 5 V. All control logic inputs
have guaranteed 2.0 V high limit when operating from + 5 V
or 5 V supplies and 1.4 V when operating from a + 3 V
supply.
•
+ 2.7 V to + 12 V single supply operation
2.5 V to 5 V dual supply operation
•
•
•
•
•
•
•
Fully specified at + 3 V, + 5 V, 5 V
100 Ω maximum on-resistance
Low voltage, 2.5 V CMOS/TTL compatible
Low charge injection (< 0.5 pC typ.)
High bandwidth: 330 MHz to 700 MHz
Low switch capacitance (Cs(off) 3 pF typ.)
RoHS
COMPLIANT
Excellent isolation and crosstalk performance (typ. 47 dB at
100 MHz)
The DG4051A, DG4052A and DG4053A switches conduct
equally well in both directions, offer rail to rail analog signal
handling and can be used both as multiplexers as well as
de-multiplexers.
< 0.5 pC low charge injection coupled with very low switch
capacitance make these products ideal for precision
instrumentation multiplexers.
•
•
16 pin SOIC, TSSOP and miniQFN package (1.8 x 2.6 mm)
Fully specified from - 40 °C to + 85 °C and - 40 °C to + 125 °C
APPLICATIONS
•
•
•
•
•
•
Precision instrumentation
Sample and hold applications
Medical instruments
Operating temperature is specified from - 40 °C to + 125 °C.
High speed communication applications
Automated test equipment
High-end data acquisition
The DG4051A, DG4052A and DG4053A are available in
16 lead SOIC, TSSOP and the space saving 1.8 x 2.6 mm
miniQFN packages.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG4053A
DG4051A
DG4052A
TSSOP16
TSSOP16
TSSOP16
1
2
3
4
5
6
X4
Y0
Y2
1
2
3
4
5
6
1
16
15
14
13
12
11
10
9
V
16
15
14
V
CC
16
15
14
13
12
11
V
CC
CC
Y1
Y0
X6
2
X2
X1
X2
Y
X
X7
3
X1
X
Y
Z1
Z
X
Y3
4
5
6
7
13
12
X0
X3
X1
X5
Y1
X0
X3
Z0
X0
A
ENABLE
ENABLE
ENABLE
ENABLE
A
B
C
11
10
9
V
V
EE
V
EE
EE
Logic
7
7
Logic
B
C
10
9
A
B
GND
8
GND
8
GND
8
Top View
Top View
Top View
ENABLE = LO, all switches are controlled by addr pins.
ENABLE = HI, all switches are off.
Document Number: 69828
S-80839-Rev. B, 21-Apr-08
www.vishay.com
1