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DG190AP/883-E3 PDF预览

DG190AP/883-E3

更新时间: 2024-11-12 09:45:23
品牌 Logo 应用领域
瑞萨 - RENESAS 光电二极管
页数 文件大小 规格书
9页 127K
描述
IC IC,ANALOG SWITCH,DUAL,SPDT,BIPOLAR/JFET,DIP,16PIN,CERAMIC, Multiplexer or Switch

DG190AP/883-E3 数据手册

 浏览型号DG190AP/883-E3的Datasheet PDF文件第2页浏览型号DG190AP/883-E3的Datasheet PDF文件第3页浏览型号DG190AP/883-E3的Datasheet PDF文件第4页浏览型号DG190AP/883-E3的Datasheet PDF文件第5页浏览型号DG190AP/883-E3的Datasheet PDF文件第6页浏览型号DG190AP/883-E3的Datasheet PDF文件第7页 
DG189/190/191  
Vishay Siliconix  
High-Speed Drivers with Dual SPDT JFET Switches  
FEATURES  
BENEFITS  
APPLICATIONS  
D Constant On-Resistance Over  
D Low Distortion  
D Audio Switching  
D Video Switching  
D Sample/Hold  
Entire Analog Range  
D Eliminates Large Signal Errors  
D High Precision  
D Low Leakage  
D Low Crosstalk  
D Rad Hardness  
D High Bandwidth Capability  
D Fault Protection  
D Guidance and Control Systems  
D Aerospace  
DESCRIPTION  
The DG189/190/191 are precision dual single-pole,  
double-throw (SPDT) analog switches designed to provide  
accurate switching of video and audio signals. This series is  
To achieve fast and accurate switch performance, each device  
comprises four n-channel JFET transistors and a TTL  
compatible bipolar driver. The driver is designed to achieve  
break-before-make switching action, eliminating the  
inadvertent shorting between channels and the crosstalk  
which would result. In the on state, each switch conducts  
current equally well in either direction. In the off condition, the  
switches will block up to 20 V peak-to-peak, with feedthrough  
of less than 60 dB at 10 MHz.  
ideally suited for applications requiring  
on-resistance over the entire analog range.  
a
constant  
The major difference in the devices is the on-resistance  
(DG189—10 , DG190—30 , DG191—75 Reduced  
errors are achieved through low leakage current (ID(on)  
< 2 nA). Applications which benefit from the flat JFET  
on-resistance include audio switching, video switching, and  
data acquisition.  
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION  
Dual-In-Line  
Flat Package  
D
S
1
1
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1
14  
13  
12  
11  
10  
9
S
D
S
3
4
4
2
2
2
NC  
IN  
1
2
3
4
5
6
7
D
D
S
3
1
D
3
V  
D
S
S
3
V
R
1
IN  
IN  
1
S
D
V
L
4
V+  
V*  
V+  
IN  
4
8
V
L
V
R
NC  
2
Top View  
D
2
S
2
Refer to JAN38510 Information, Military Section  
*Common to Substrate and Case  
Top View  
TRUTH TABLE  
Logic  
SW1, SW2  
SW3, SW4  
0
1
OFF  
ON  
ON  
OFF  
Logic “0” v 0.8 V  
Logic “1” w 2.4 V  
Document Number: 70034  
S-51140—Rev. D, 20-Jun-05  
www.vishay.com  
1

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