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DEI1148-QES-G PDF预览

DEI1148-QES-G

更新时间: 2024-01-18 02:47:20
品牌 Logo 应用领域
DEIAZ 信息通信管理接口集成电路
页数 文件大小 规格书
8页 532K
描述
OCTAL ARINC 429 LINE RECEIVER

DEI1148-QES-G 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:MQFP-44针数:44
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.52
其他特性:ALSO OPERATE WITH 5V SUPPLY差分输出:NO
输入特性:DIFFERENTIAL SCHMITT TRIGGER接口集成电路类型:LINE RECEIVER
接口标准:ARINC 429JESD-30 代码:S-PQFP-G44
JESD-609代码:e3长度:10 mm
湿度敏感等级:3功能数量:8
端子数量:44最高工作温度:85 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装形状:SQUARE
封装形式:FLATPACK峰值回流温度(摄氏度):260
认证状态:Not Qualified最大接收延迟:200 ns
接收器位数:8座面最大高度:2.45 mm
最大供电电压:3.63 V最小供电电压:2.97 V
标称供电电压:3.3 V电源电压1-最大:5.5 V
电源电压1-分钟:4.5 V电源电压1-Nom:5 V
表面贴装:YES技术:BICMOS
温度等级:OTHER端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:10 mmBase Number Matches:1

DEI1148-QES-G 数据手册

 浏览型号DEI1148-QES-G的Datasheet PDF文件第1页浏览型号DEI1148-QES-G的Datasheet PDF文件第2页浏览型号DEI1148-QES-G的Datasheet PDF文件第3页浏览型号DEI1148-QES-G的Datasheet PDF文件第5页浏览型号DEI1148-QES-G的Datasheet PDF文件第6页浏览型号DEI1148-QES-G的Datasheet PDF文件第7页 
Table 3: Electrical Characteristics  
Conditions: Temperature: -55 °C to +85 °C (-QES); -55 °C to +125 °C (-QMS)  
VDD = +5 V ±10% or 3.3 V ±10%  
PARAMETER  
TEST CONDITION  
ARINC INPUTS  
SYMBOL  
MIN  
MAX  
UNITS  
VA – VB = Logic +1  
VA – VB = Logic -1  
OUTA = 1  
OUTB = 1  
V+1  
V-1  
6.5  
13  
V
V
-6.5  
-13  
OUTA = 0  
OUTB = 0  
VA – VB = Logic Null  
Input Hysteresis  
VNULL  
VHY  
-2.5  
2.0  
-20  
2.5  
4.0  
+20  
V
V
V
Input Common Mode  
Voltage Range  
Logic +1, Null, Logic -1  
VCM  
Input Resistance  
INA to INB  
VDD open,  
Shorted to VSS or +5 V (1)  
RIN  
RS  
280  
140  
kW  
kW  
pF  
pF  
Input Resistance  
INA or INB to VSS  
VDD open,  
Shorted to VSS or +5 V  
Input Capacitance  
INA to INB  
VDD open,  
Shorted to VSS or +5 V (1)  
CIN  
CS  
10  
10  
Input Capacitance  
INA or INB to VSS  
VDD open,  
Shorted to VSS or +5 V (1)  
LOGIC INPUTS  
Logic 0 Voltage  
Logic 1 Voltage  
Logic 0 Current  
Logic 1 Current  
VIL  
VIH  
IIL  
0.8  
V
V
2.0  
2.4  
VIL = 0.8  
VIH = 2.0  
25  
25  
µA  
µA  
IIH  
LOGIC OUTPUTS  
IOH = -5 mA (VDD = 5.0 V)  
IOH = -5 mA (VDD = 3.3 V)  
TTL Compatible  
OUTPUT HIGH VOLTAGE  
TTL  
VOH  
VOL  
V
OUTPUT LOW VOLTAGE  
TTL  
IOL = 5mA (VDD = 5.0 V)  
0.4  
V
V
V
OUTPUT HIGH VOLTAGE  
CMOS  
IOH = 100 µA  
CMOS Compatible  
VDD –  
50mV  
VOH  
VOL  
OUTPUT LOW VOLTAGE  
CMOS  
IOL = 100 µA  
CMOS Compatible  
VSS+  
50mV  
SUPPLY CURRENT  
Data Rate = 0 MHZ,  
INA/B = open,  
OUTA/B = open,  
VDDCurrent  
IDD  
1.5  
8.5  
mA  
VDD = 5.5 V or 3.63 V  
Notes:  
1. Guaranteed by design, not production tested.  
2. Current flowing into device is positive. Current flowing out of device is negative. All  
voltages are with respect to VSS unless otherwise noted.  
©2019 Device Engineering Inc.  
Page 4 of 8  
DS-MW-01148-01 Rev B  
01/08/2019  

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