Datasheet > DEI1117-QES-G

DEI1117-QES-G

更新时间： 2024-01-26 17:09:52

品牌	Logo	应用领域
DEIAZ		驱动接口集成电路驱动器
页数	文件大小	规格书
14页	587K
描述
Transceiver Family

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技术参数
数据手册

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DEI1117-QES-G 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	QFP	包装说明：	QFP,
针数：	44	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.69	差分输出：	NO
驱动器位数：	1	输入特性：	DIFFERENTIAL
接口集成电路类型：	LINE TRANSCEIVER	接口标准：	ARINC 429
JESD-30 代码：	S-PQFP-G44	JESD-609代码：	e3
长度：	10 mm	功能数量：	1
端子数量：	44	最高工作温度：	85 °C
最低工作温度：	-55 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装形状：	SQUARE
封装形式：	FLATPACK	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	最大接收延迟：
接收器位数：	2	座面最大高度：	2.5 mm
最大供电电压：	3.63 V	最小供电电压：	2.97 V
标称供电电压：	3.3 V	电源电压1-最大：	5.5 V
电源电压1-分钟：	4.5 V	电源电压1-Nom：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	OTHER	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10 mm	Base Number Matches：	1

DEI1117-QES-G 数据手册

Table 1: Pin Definitions

DEFINITION

SYMBOL

V_DD

GND

Power Input. +5VDC ±10%

Power Return and Signal Ground.

DI1(A)

DI1(B)

DI2(A)

DI2(B)

/LDCW

SEL

ARINC 429 Input. Receiver Channel 1, “A” input

ARINC 429 Input. Receiver Channel 1, “B” input

ARINC 429 Input. Receiver Channel 2, “A” input

ARINC 429 Input. Receiver Channel 2, “B” input

Logic Input. Load Control Register. A Low input pulse loads the Control Register from D[15:0].

Logic Input. Receiver word select. A Low input selects receiver Word 1; Hi selects Word 2 to be read

on D [15:0] port.

/LD1

/LD2

Logic Input. Load Transmitter Word 1. A Low input pulse loads Word 1 into the Transmitter FIFO

from D [15:0].

Logic Input. Load Transmitter Word 2. A Low input pulse loads Word 2 into the Transmitter FIFO

from D [15:0].

ENTX

Logic Input. Enable Transmitter. A Hi input enables the Transmitter to send data from the Transmitter

FIFO. This must be Low while writing data into Transmitter FIFO. Transmitter memory is cleared by

high-to-low transition.

D[15:0]

/OE1

Logic Input / Tri-state Output. This 16-bit bi-directional data port is the uP data interface. Receiver

data is read from this port. Control Register and Transmitter FIFO data is written into this port.

Logic Input. Receiver 1 Output Enable. A Low input enables the D [15:0] port to output Receiver 1

data. Word 1 or Word 2 will be output as determined by the SEL input.

/OE2

Logic Input. Receiver 2 Output Enable. A Low input enables the D [15:0] port to output Receiver 2

data. Word 1 or Word 2 will be output as determined by the SEL input.

/DR1

/DR2

TXR

Logic Output. Data Ready, Receiver 1. A Low output indicates valid data in receiver 1.

Logic Output. Data Ready, Receiver 2. A Low output indicates valid data in receiver 2.

Logic Output. Transmitter Ready. A Hi output indicates the Transmitter FIFO is empty and ready to

accept new data.

DO(A), DO(B)

Logic Outputs. Transmitter serial data outputs.

This is a return-to-zero format signal which will normally feed an ARINC 429 Line Driver IC.

A Hi output on DO(A) indicates the Transmitter data bit is a 1.

A Hi output on DO(B) indicates the Transmitter data bit is a 0.

The signal returns to zero for second half of bit time.

TXCK

Logic Output. Transmitter Clock. This outputs a clock frequency equal to the transmit data rate. The

clock is always enabled and in phase with the data. The output is Hi during the first half of the data bit

time.

1MCK

/MR

Logic Input. External Clock. Master clock used by both the Receivers and Transmitter. The 1MHz

rate is an X10 clock for the HI data rate (100 kbps), and a X80 clock for LO data rate (12.5 kbps).

Logic Input. Master Reset. A Lo input resets the Transmitter FIFO, bit counters, word counter, gap

timers, /DRx, and TXR. The Control Register is not affected. Used on power up and system reset.

/DBCEN

Logic Input with internal pull up to V_DD. Data Bit Control Enable. A Low input enables the

transmitter parity bit control function as defined by control register bit 4 (PAREN). A Hi input forces

transmitter parity bit insertion regardless of PAREN value. The pin is normally left open or tied to

ground.

DS-MW-01117-01 Rev B

02/09/2012

Page 2 of 14

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型号	品牌	描述	获取价格	数据表
DEI1117-QMS-G	DEIAZ	Transceiver Family	获取价格
DEI1148	DEIAZ	OCTAL ARINC 429 LINE RECEIVER	获取价格
DEI1148-QES-G	DEIAZ	OCTAL ARINC 429 LINE RECEIVER	获取价格
DEI1148-QMS-G	DEIAZ	OCTAL ARINC 429 LINE RECEIVER	获取价格
DEI1160	DEIAZ	PROGRAMMABLE GND/OPN & 28V/OPN DISCRETE INPUT INTERFACE IC	获取价格
DEI1160A	DEIAZ	PROGRAMMABLE GND/OPN & 28V/OPN DISCRETE INPUT INTERFACE IC	获取价格

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