5秒后页面跳转
DEI1116-QES-G PDF预览

DEI1116-QES-G

更新时间: 2024-02-08 10:08:21
品牌 Logo 应用领域
DEIAZ 驱动接口集成电路驱动器
页数 文件大小 规格书
14页 587K
描述
Transceiver Family

DEI1116-QES-G 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:QFP包装说明:GREEN, PLASTIC, MO-112AA-1, QFP-44
针数:44Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.69差分输出:NO
驱动器位数:1输入特性:DIFFERENTIAL
接口集成电路类型:LINE TRANSCEIVER接口标准:ARINC 429
JESD-30 代码:S-PQFP-G44JESD-609代码:e3
长度:10 mm功能数量:1
端子数量:44最高工作温度:85 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装形状:SQUARE
封装形式:FLATPACK峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified最大接收延迟:
接收器位数:2座面最大高度:2.5 mm
最大供电电压:3.63 V最小供电电压:2.97 V
标称供电电压:3.3 V电源电压1-最大:5.5 V
电源电压1-分钟:4.5 V电源电压1-Nom:5 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10 mmBase Number Matches:1

DEI1116-QES-G 数据手册

 浏览型号DEI1116-QES-G的Datasheet PDF文件第1页浏览型号DEI1116-QES-G的Datasheet PDF文件第2页浏览型号DEI1116-QES-G的Datasheet PDF文件第3页浏览型号DEI1116-QES-G的Datasheet PDF文件第5页浏览型号DEI1116-QES-G的Datasheet PDF文件第6页浏览型号DEI1116-QES-G的Datasheet PDF文件第7页 
Table 3: Absolute Maximum Ratings  
PARAMETER  
Supply Voltage  
DC Input Voltage, Logic inputs  
SYMBOL  
VDD  
VIN-logic  
MIN  
-0.5  
-0.6  
MAX  
+7.0  
VCC+0.6  
UNITS  
V
V
DC Input Voltage, RX pins: DI[1A/1B/2A/2B]  
DEI1116  
VIN-rx  
±40  
±40  
V
DEI1117 with external 10K ohm series resistors  
VIN-rxe  
DO160 Sect 22 Lightning Immunity pin injection  
WF4 & WF5A  
±300  
±600  
WF3  
Clamp diode current, any pin except RX inputs  
DC Output Current per pin  
Storage Temperature  
±25  
±25  
+150  
+145  
mA  
mA  
°C  
Tstg  
-65  
Junction Temperature, operating  
TJmax  
°C  
Table 4: AC Electrical Characteristics  
SYMBOL  
PARAMETER  
1MCK Frequency  
1MCK Duty Cycle  
1MCK Rise/Fall Time  
Data Rate 100kbpsData Rate 12.5kbps  
MIN  
0.99  
40  
MAX  
1.01  
60  
MIN  
0.99  
40  
MAX  
1.01  
60  
UNITS  
MHz  
%
ns  
ns  
kbps  
f1MCK  
CKDC  
TCRF  
TMR  
10  
10  
Master Reset Pulse Width  
Transmitter Data Rate (1MCK = 1MHz)  
200  
99  
200  
12.4  
TDR  
101  
105  
12.6  
14.5  
Receiver Data Rate (1MCK = 1MHz),  
RDR  
95  
8.0  
kbps  
(DATA = 50% BIT/ 50% NULL TIME)  
Functional Description:  
Table 5: Control Register Format  
The DEI1116/1117 supports a number of various options  
which are selected by data written into the control register.  
Data is written into the control register from the 16-bit data  
bus when the /LDCW signal is pulsed to a logic “0”. The  
twelve control bits control the following functions:  
BIT  
SYMBOL  
WLSEL  
RCVSEL  
TXSEL  
PARCK  
Y2  
BIT  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
SYMBOL  
X1  
SDENB1  
/SLFTST  
PAREN  
NOT USED  
NOT USED  
NOT USED  
NOT USED  
D15 (MSB)  
D14  
D13  
D12  
D11  
D10  
D9  
D8  
1) Word Length (32 or 25 bits)  
2) Transmitter bit 32 (Parity or Data)  
3) Wrap around self test.  
4) Source Destination code checking of received data.  
5) Transmitter parity (even or odd)  
X2  
6) Transmitter and Receiver data rate (100 or 12.5 kbps)  
SDENB2  
Y1  
© 2012 Device Engineering Inc.  
DS-MW-01117-01 Rev B  
02/09/2012  
Page 4 of 14  

与DEI1116-QES-G相关器件

型号 品牌 描述 获取价格 数据表
DEI1116-QMS-G DEIAZ Transceiver Family

获取价格

DEI1117-PES-G DEIAZ Transceiver Family

获取价格

DEI1117-PMS-G DEIAZ Transceiver Family

获取价格

DEI1117-QES-G DEIAZ Transceiver Family

获取价格

DEI1117-QMS-G DEIAZ Transceiver Family

获取价格

DEI1148 DEIAZ OCTAL ARINC 429 LINE RECEIVER

获取价格