Datasheet > DDX4100ERRATA

DDX4100ERRATA

更新时间： 2024-09-14 23:46:47

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DDX4100 Errata January 17 2002

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DDX4100ERRATA 数据手册

DDX-4100 Errata

DDX Multichannel

Digital Audio Processor

ERRATA

A] When using the sample rate converter (SRC), it is mandatory to apply a

valid input signal to the DDX-4100 prior to unmuting. Failure to do so will

result in large DC offsets applied to speaker outputs which may damage

loudspeakers.

To ensure proper operation using the S/PDIF input, be sure to poll the “S/PDIF

Status” bit (register 0x77, bit 1 which determines S/PDIF lock) indicating a valid

input signal prior to unmuting. Bit 1 will report logic ‘0’ for a valid S/PDIF input

signal or logic ‘1’ for an invalid signal. Delay unmuting until after a valid signal is

detected.

To ensure proper operation using the serial I2S inputs or AC97, valid clock

signals must be applied to DDX-4100 pins 3,4 (LRCKI/SYNC, BICKI/BIT_CLK)

prior to unmuting. The “SRC Status” bit (register 0x77, bit 0 which determines

SRC lock), does not provide a correct indication prior to receiving a valid input

signal. The “SRC Status” bit 0 will indicate SRC lock , logic ‘0’, whether or not

valid input signals are applied. Subsequent to receiving a valid input signal, the

“SRC Status” bit operates as intended, i.e. removing the input signal will cause

an out-of-lock indication.

B] It is recommended to configure the device using a 24.576MHz crystal.

Be sure the “PLL_Factor” bit in CRA is cleared (Configuration Register A,

Subaddress 0x5B, bit 7= ‘0’). This is the default value following hardware

RESET (pin 7) being deasserted or writing to the “Reset Register” (Subaddress

0x00) via I²C. The alternate 6.144MHz crystal is not recommended. When

using the 6.144MHz crystal, difficulties have been observed following power-up

which may appear as I²C related. These include unexpected muting or failure to

un-mute when commanded, poor S/N ratio which improves after power cycling,

or high DC output with no audio. These operational difficulties can be solved by

substituting a 24.576MHz crystal and clearing the PLL_Factor.

C] V_DDshould be limited to 3.4V maximum for proper operation.

129 Morgan Drive, Norwood MA 02062

- 1 -

voice: (781) 551-9450 fax: (781) 440-9528 email: sales@apogeeddx.com

January 2002

DOC #07010002-03

12 3

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与DDX4100ERRATA相关器件

型号	品牌	获取价格	描述	数据表
DDX50P-0L2-A191-K87-146	ITT	获取价格	D Subminiature Connector, 50 Contact(s), Male, Solder Terminal, Plug,
DDX50P-0L2-K87-146	ITT	获取价格	D Subminiature Connectors
DDX-50P-0L4-A191-K87-146	ITT	获取价格	D Subminiature Connector
DDX50PA191K87	ITT	获取价格	D Subminiature Connector, 50 Contact(s), Male, Solder Terminal, Plug,
DDX50PK87	ITT	获取价格	D Subminiature Connectors
DDX50P-OL2-A191-K87-146	ITT	获取价格	D Subminiature Connector, 50 Contact(s), Male, Solder Terminal, Plug,
DDX50P-OL2-K87-146	ITT	获取价格	D Subminiature Connector, 50 Contact(s), Male, Solder Terminal, Plug,
DDX50P-OL4-A191-K87-146	ITT	获取价格	D Subminiature Connector, 50 Contact(s), Male, Solder Terminal, Plug,
DDX50P-OL4-K87-146	ITT	获取价格	D Subminiature Connector, 50 Contact(s), Male, Solder Terminal, Plug,
DDX-50S-0L4-A197-146	ITT	获取价格	D Subminiature Connector

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