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DAC7545LU PDF预览

DAC7545LU

更新时间： 2024-01-02 21:27:21
品牌 Logo 应用领域
德州仪器 - TI 转换器数模转换器微处理器光电二极管
页数 文件大小 规格书
12页 383K
描述
CMOS 12-Bit Multiplying DIGITAL-TO-ANALOG CONVERTER Microprocessor Compatible

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DAC7545LU 技术参数

是否Rohs认证：不符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.75
Is Samacsys：N转换器类型：D/A CONVERTER
输入位码：BINARY, OFFSET BINARY输入格式：PARALLEL, WORD
JESD-30 代码：R-CDIP-T20JESD-609代码：e0
最大线性误差 (EL)：0.0488%位数：12
功能数量：1端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：DIP
封装等效代码：DIP20,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：5/15 V
认证状态：Not Qualified最大稳定时间：2 µs
子类别：Other Converters最大压摆率：2 mA
标称供电电压：15 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
Base Number Matches：1

DAC7545LU 数据手册

 浏览型号DAC7545LU的Datasheet PDF文件第3页浏览型号DAC7545LU的Datasheet PDF文件第4页浏览型号DAC7545LU的Datasheet PDF文件第5页浏览型号DAC7545LU的Datasheet PDF文件第7页浏览型号DAC7545LU的Datasheet PDF文件第8页浏览型号DAC7545LU的Datasheet PDF文件第9页 
DIGITALLY-CONTROLLED GAIN BLOCK  
reference applications and low-bandwidth requirement; the  
OPA37 has low VOS and does not require an offset trim. For  
wide bandwidth, high slew rate, or fast-settling applications, the  
OPA604 or 1/2 OPA2604 are recommended.  
Figure 4 shows a circuit for a digitally-controlled gain block.  
The feedback for the op amp is made up of the FET switch  
and the R-2R ladder. The input resistor to the gain block is  
the RFB of the DAC7545. As the FET switch is in the  
feedback loop, a zero code into the DAC will result in the op  
amp having no feedback, and a saturated op amp output.  
Unused digital inputs must be connected to VDD or to DGND,  
this prevents noise from triggering the high impedance digital  
input. It is suggested that the unused digital inputs also be  
given a path to ground or VDD through a 1mW resistor to  
prevent the accumulation of static charge if the PC card is  
unplugged from the system. In addition, in systems where  
the AGND to DGND connection is on a backplane, it is  
recommended that two diodes be connected in inverse  
parallel between AGND and DGND.  
–VIN  
VOUT  
=
DB11 DB10 DB9  
DB0  
+
+
+ ••• +  
2
4
8
4096  
VIN  
DB0-DB11  
WR CS  
INTERFACING  
RFB  
20  
17 16  
TO MICROPROCESSORS  
The DAC7545 can be directly interfaced to either an 8- or 16-  
bit microprocessor through its 12-bit wide data latch using  
the CS and WR controls.  
+5V  
OUT 1  
18  
19  
DAC7545  
AGND  
DGND  
NOTE: There must be  
at least 1LSB loaded in  
the DAC or the amp will  
saturate due to the lack  
of feedback.  
An 8-bit processor interface is shown in Figure 5. It uses two  
memory addresses: one for the lower 8 bits and one for the  
upper 4 bits of data into the DAC via the latch.  
VOUT  
OPA111  
A15  
Address Bus  
A0  
FIGURE 4. Digitally Controlled Gain Block.  
(1)  
Q0  
Address  
Decode  
CS  
CS  
Latch  
WR  
(2)  
Q1  
APPLICATION HINTS  
DB11  
DB8  
4
4
8
CPU  
CMOS DACs, such as the DAC7545, exhibit a code-depen-  
dent out resistance. The effect of this is a code-dependent  
differential nonlinearity at the amplifier output that depends on  
the offset voltage, VOS, of the amplifier. Thus linearity depends  
upon the potential of OUT 1 and AGND being exactly equal to  
each other. Usually the DAC is connected to an external op  
amp with the noninverting input connected to AGND. The op  
amp selected should have a low input bias current and low VOS  
and VOS drift over temperature. The op amp offset voltage  
should be less than (25 • 10–6)(VREF) over operating conditions.  
Suitable op amps are the OPA37 and the OPA627 for fixed  
DAC7545  
WR  
WR  
DB7  
DB0  
DB7  
DB0  
8-Bit Data Bus  
NOTES: (1) Q0 = decoded address for DAC.  
(2) Q1 = decoded address for latch.  
FIGURE 5. 8-Bit Processor Interface.  
DAC7545  
6
SBAS150A  
www.ti.com  
1...3456789...12

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