ABSOLUTE MAXIMUM RATINGS(1)
TA = +25°C, unless otherwise noted.
ELECTROSTATIC
DISCHARGE SENSITIVITY
VDD to DGND ........................................................................... –0.3V, +17
Digital Input to DGND ............................................................... –0.3V, VDD
VRFB, VREF, to DGND ........................................................................ ±25V
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
V
PIN 1 to DGND ........................................................................ –0.3V, VDD
AGND to DGND ........................................................................ –0.3V, VDD
Power Dissipation: Any Package to +75°C .................................... 450mW
Derates above +75°C by ................................ 6mW/°C
Operating Temperature:
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
Commercial J, K, L, and GL ........................................... –40°C to +85°C
Storage Temperature ...................................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTE: (1) Stresses above those listed above may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at
these or any other condition above those indicated in the operational sections of
thisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditions
for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
SPECIFIED
RELATIVE
PRODUCT ACCURACY (LSB)
GAIN ERROR (LSB)
VDD = +5V
PACKAGE
PACKAGE-LEAD DESIGNATOR(1)
TEMPERATURE PACKAGE
RANGE MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
DAC7545
±2
±1
±20
±10
±5
SO-20
DW
"
–40°C to +85°C DAC7545JU
DAC7545JU
Rails, 38
Rails, 38
Rails, 38
Rails, 38
"
"
SO-20
"
"
DAC7545KU DAC7545KU
DAC7545
"
±1/2
±1/2
DW
"
–40°C to +85°C DAC7545LU DAC7545LU
±2
"
DAC7545GLU DAC7545GLU
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
PIN CONNECTIONS
Top View
SO
OUT 1
AGND
DGND
(MSB) DB11
DB10
1
2
3
4
5
6
7
8
9
20 RFB
19 VREF
18 VDD
17 WR
16 CS
DAC7545
DB9
15 DB0 (LSB)
14 DB1
13 DB2
12 DB3
11 DB4
DB8
DB7
DB6
DB5 10
WRITE CYCLE TIMING DIAGRAM
tCS
tCH
CS
VDD
0
Mode Selection
Write Mode
Hold Mode
CS and WR low, DAC responds
Data Bus (DB0-DB11) inputs.
Either CS or WR high, data bus to
(DB0-DB11) is locked out; DAC
holds last data present when
WR or CS assumed high state.
tWR
WR
VDD
0
tDH
tDS
NOTES: VDD = +5V, tR = tF = 20ns. VDD = +15V, tR = tF = 40ns. All inputs signal
rise and fall times measured from 10% to 90% of VDD. Timing measurement
reference level is (VIH + VIL)/2.
VDD
0
Data In
(DB0-DB11
VIH
VIL
Data
Valid
)
DAC7545
2
SBAS150A
www.ti.com