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DAC-12100LE PDF预览

DAC-12100LE

更新时间: 2024-10-29 00:54:27
品牌 Logo 应用领域
达特尔 - DATEL 信息通信管理转换器
页数 文件大小 规格书
7页 334K
描述
12-Bit, 100MHz, Low-Power D/A Converters

DAC-12100LE 数据手册

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DAC-12100  
12-Bit, 100MHz, Low-Power D/A Converters  
FEATURES  
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100MHz conversion rate  
Low power, 650mW, typical  
Low glitch energy, 3.0pV-s  
Excellent dynamic specifications  
TTL/CMOS compatible inputs  
20ns settling time  
PRODUCT OVERVIEW  
The DAC-12100 is a 12-bit, ultra high speed, current The architecture employs an R/2R resistor network  
output digital-to-analog converter. This TTL/CMOS  
compatible device converts at a rate of 100MHz  
and features a 3.0 pV-s glitch energy and excellent  
frequency domain specifications. The DAC-12100  
develops complementary current outputs of 0 to  
–20.48mA and can directly drive 50 Ohm loads.  
The excellent dynamic specifications (to Nyquist at  
fOUT=2.02MHz) include an SFDR of –85dB. Static  
performance includes maximum over temperature  
specifications of +/- 1.75LSB and +/-1LSB for  
integral and differential nonlinearity, respectively.  
and a segmented switching current cell arrange-  
ment to reduce glitch. Laser trimming assures that  
12-bit linearity is achieved and maintained over the  
transfer curve. It also incorporates a 12-bit input  
data register and bandgap voltage reference with a  
buffer amplifier.  
Packaged in a hermetic ceramic LCC package  
(0.450 X 0.450 inches)  
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Standard versions come with solder dipped leads  
Low cost  
The DAC-12100 runs on +5V and –5.2V supplies  
and dissipates a maximum of 800mW. It is avail-  
able in a 28-pin CLCC solder dipped leads package  
with an operating temperature range of 0 to 70°C  
and –55 to +125°C. If needed a RoHS version is  
Models available in commercial (0 to + 70°C), indus-  
trial (–40 to +100°C), or military (–55 to +125°C)  
operating temperature ranges  
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Full 883 and LM/QL versions available  
If needed a ROHS version is available  
The DAC-12100 achieves low power and high speed available upon request.  
performance from an advanced BiCMOS process.  
FUNCTIONAL BLOCK DIAGRAM  
BIT 1 ( MSB) 28  
BIT 2  
BIT 3  
BIT 4  
BIT 5  
BIT 6  
BIT 7  
BIT 8  
BIT 9  
BIT 10  
BIT 11  
1
2
3
8 LSBs  
CURRENT  
CELLS  
4
DATA  
BUFFER  
LEVEL  
SHIFTER  
12-BIT  
MASTER  
REGISTER  
SLAVE  
REGISTER  
5
R/2R  
NETWORK  
6
7
8
15  
UPPER  
4-BIT  
DECODER  
14  
16  
IOUT  
9
SWITCHED  
CURRENT  
CELLS  
10  
BIT 12 (LSB) 11  
IOUT  
REF CELL  
17 Ref In  
Data Clock 26  
Ω
25  
+
OVERDRIVEABLE  
VOLTAGE  
REFERENCE  
CTRL  
OUT  
18  
12,21  
–5.2V  
DIGITAL  
SUPPLY  
15,25  
–5.2V  
ANALOG  
SUPPLY  
27  
DGND  
RefGND 22  
23  
+5V SUPPLY  
13  
AGND  
20  
REF OUT  
24  
RSET  
19  
CTRL  
IN  
Figure 1. Functional Block Diagram  
DATEL, Inc. 11 Cabot Boulevard, Manseld, MA 02048-1151 USA  
Tel: (508) 339-3000  
www.datel.com  
e-mail: help@datel.com  
26 Jun 2015 MDA_DAC-12100.B03 Page 1 of 7  

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