Datasheet > D70325

D70325

更新时间： 2024-11-02 05:34:43

品牌	Logo	应用领域
日电电子 - NEC		微控制器
页数	文件大小	规格书
80页	534K
描述
V25+TM 16/8-BIT SINGLE-CHIP MICROCONTROLLER

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D70325 数据手册

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD70325

V25+^TM

16/8-BIT SINGLE-CHIP MICROCONTROLLER

The µPD70325 (V25+) is a single-chip microcontroller on which 16-bit CPU, RAM, serial interface, timer, DMA

controller, interrupt controller, etc. are all integrated. The µPD70325 is software compatible with the 16/8-bit single-

chip microcontroller µPD70320 (V25^TM). The V25+ greatly improves the DMA responsivity and transfer rate compared

to the V25.

FEATURES

• Software compatible with V25

• Software compatible with µPD70108/70116 (in native mode) (some instructions added)

• Internal 16-bit architecture and external 8-bit data bus

• 3-stage pipeline method

• Minimum instruction cycle : 250 ns/8 MHz (external 16 MHz)

: 200 ns/10 MHz (external 20 MHz)

• Memory space 1 Mbyte

• On-chip RAM : 256 words × 8 bits

• Register bank (memory mapped method) : 8 banks

• Input port (port T) with comparator : 8 bits

• I/O lines (input port : 4 bits, input/output ports : 20 bits)

• Serial interface : 2 channels

•

Internal dedicated baud rate generator

•

Asynchronous mode and I/O interface mode

• Interrupt controller

•

Programmable priority (8 levels)

•

3 types of interrupt response method

Vectored interrupt function, register bank switching function, macro service function

• DRAM and pseudo SRAM refreshing function

• DMA controller : 2 channels

•

4 types of DMA transfer mode

•

Transfer rate Maximum 4 Mbytes/second (when stop control is not executed by DMARQ pin in demand release

mode)

Maximum 2 Mbytes/second (when stop control is executed by DMARQ pin in demand release

mode, or burst mode)

Address pointer (linear) : 20 bits

Terminal counter : 16 bits

•

• 16-bit timer : 2 channels

• Time base counter (20 bits) : 1 channel

• On-chip clock generator

• Programmable wait function

• Standby function (STOP, HALT)

The information in this document is subject to change without notice.

Document No. U12850EJ7V0DS00 (7th edition)

Date Published November 1997 N

Printed in Japan

The mark

shows major revised points.

1995

1996

12 3 4 5 6 7...80

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