Datasheet > D6301

D6301

更新时间： 2024-11-15 21:55:27

品牌	Logo	应用领域
其他 - ETC		时钟发生器动态存储器
页数	文件大小	规格书
1页	55K
描述
Pentium/SDRAM Clock Generator with Integrated Buffers

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中文翻译

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数据手册

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D6301 数据手册

PLL52C63-01

P e n tiu m /S DRAM Clo c k Ge n e ra to r with In te g ra te d Bu ffe rs

FEATURES

PIN INFORMATION

n Generates all clock frequencies for Pentium (II), AMD

and Cyrix system requiring multiple CPU clocks.

n Supports upto16Synchronous CPUclocks (4CPU and

12 SDRAM) and 7 Synchronous PCI BUS clocks.

n Two14.318Mhzreference clocks andone 2.5VIOAPIC

n One 24Mhz floppy clock and one 48Mhz USB clock.

n Power management control pins to stop CPU, SDRAM

or PCI BUS clocks.

n Supports 2-wire I2C serial bus interface.

n 50% duty cycle with low jitter

n Mixedvoltage supportfrom3.0to5Vor(VDDq2=2.5V)

n Available in 300mil 48 pin SSOP.

FREQUENCY SELECTION (MHz)

F0 PCLK/SDRAM

BCLK

100

83.3

68.5

Note: F2,F1,F0 and MODE are selectable only during power-on. They are

HIGH by default and LOW when 10K W Pull down is attached.

41.6

34.2

27.5

37.5

I/O MODE CONFIGURATION

MODE

PIN15

BCLK5

PCISTP

PIN46

REF1

1 (OUTPUT)

0 (INPUT)

66.6

33.3

CPUSTP

BLOCK DIAGRAM

45437 Warm Springs Blvd., Fremont, California 94539, TEL 510-492-0990 FAX 510-492-0991

9704.Rev.1C Page 1

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