5秒后页面跳转
捷配首页

Datasheet > CYW312OXC
CYW312OXC PDF预览

CYW312OXC

更新时间： 2024-01-28 14:04:15
品牌 Logo 应用领域
SPECTRALINEAR /
页数 文件大小 规格书
19页 193K
描述
FTG for VIA⑩ K7 Series Chipset with Programmable Output Frequency

阅读下载

获取价格

CYW312OXC 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：SSOP包装说明：SSOP, SSOP48,.4
针数：48Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.51Is Samacsys：N
其他特性：ALSO REQUIRES 2.5V SUPPLYJESD-30 代码：R-PDSO-G48
JESD-609代码：e4长度：15.875 mm
湿度敏感等级：3端子数量：48
最高工作温度：70 °C最低工作温度：
最大输出时钟频率：200 MHz封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP48,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：2.5/3.3 V
主时钟/晶体标称频率：14.31818 MHz认证状态：Not Qualified
座面最大高度：2.794 mm子类别：Clock Generators
最大供电电压：3.465 V最小供电电压：3.135 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：20宽度：7.5057 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches：1

CYW312OXC 数据手册

 浏览型号CYW312OXC的Datasheet PDF文件第1页浏览型号CYW312OXC的Datasheet PDF文件第3页浏览型号CYW312OXC的Datasheet PDF文件第4页浏览型号CYW312OXC的Datasheet PDF文件第5页浏览型号CYW312OXC的Datasheet PDF文件第6页浏览型号CYW312OXC的Datasheet PDF文件第7页 
W312-02  
I
Pin Definitions  
Pin  
Type  
Pin Name  
Pin No.  
Pin Description  
REF0/FS0  
48  
I/O  
Reference Clock Output 0/Frequency Select 0: 3.3V 14.318-MHz clock  
output. REF0 will be disabled when REF_STOP# is active. This pin also serves  
as the select strap to determines device operating frequency as described in  
Table 5.  
REF1/FS1  
47  
I/O  
Reference Clock Output 0/Frequency Select 1: 3.3V 14.318-MHz clock  
output. REF1 will be disabled when REF_STOP# is active. This pin also serves  
as the select strap to determines device operating frequency as described in  
Table 5.  
REF2  
X1  
46  
3
I/O  
Reference Clock Output 2: 3.3V 14.318-MHz clock output. REF2 will be  
disabled when REF_STOP# is active.  
I
I
I
Crystal Input: This pin has dual functions. It can be used as an external  
14.318-MHz crystal connection or as an external reference frequency input.  
X2  
4
Crystal Output: An input connection for an external 14.318-MHz crystal  
connection. If using an external reference, this pin must be left unconnected.  
PCI_F/FS4  
9
Free-Running PCI Clock/Frequency Select 4: 3.3V 33-MHz free running PCI  
clock output. This pin also serves as the select strap to determines device  
operating frequency as described in Table 5.  
PCI_0/SEL24_48#  
10  
I/O  
PCI Clock 0/Select 24 or 48 MHz: 3.3V 33-MHz PCI clock outputs. This output  
will be disabled when PCI_STOP# is active. This pin also serves as the select  
strap to determine device operating frequency of 24_48MHz output.  
PCI1:8  
PCI9_E  
AGP0:2  
11, 13, 14, 16,  
17, 18, 20, 21  
O
O
O
PCI Clock 1 through 8: 3.3V 33-MHz PCI clock outputs. PCI1:8 will be disabled  
when PCI_STOP# is active.  
22  
Early PCI Clock 9: 3.3V 33-MHz PCI clock outputs. PCI9_E will be disabled  
when PCI_STOP# is active.  
26, 27, 28  
AGP Clock 0 through 2: 3.3V 66-MHz clock outputs. The operating frequency  
is controlled by FS0:4 (see Table 5). AGP0:2 will be disabled when  
AGP_STOP# is active.  
48MHz/FS2  
6
7
I/O  
I/O  
48-MHz Output/Frequency Selection 3: 3.3V 48-MHz non-spread spectrum  
output. 48MHz will bedisabledwhenREF_STOP# is active. This pinalsoserves  
as the select strap to determine device operating frequency as described in  
Table 5.  
24_48MHz/FS3  
24 or 48-MHz Output/Select 24 or 48 MHz: 3.3V 24 or 48-MHz non-spread  
spectrum output. 24_48MHz will be disabled when REF_STOP# is active. This  
pin also serves as the select strap to determine device operating frequency as  
described in Table 5.  
RST#  
24  
O
Reset#: Open-drain RESET# output.  
(open-d  
rain)  
CPUT0, CPUC0  
42, 41  
39, 38  
36  
O
CPU Clock Output 0: CPUT0 and CPUC0 are the differential CPU clock  
(open-d outputs for the K7 processor. They are open-drain outputs.  
rain)  
CPUT_CS,  
CPUC_CS  
O
CPU Clock Output for Chipset: CPUT_CS and CPUC_CS are the differential  
CPU clock outputs for the chipset. They are push-pull outputs. These outputs  
will be disabled when CPU_STOP# is active.  
CPU_STOP#  
I
CPU STOP Input: This input will disable CPUT_CS and CPUC_CS when it is  
active.  
PCI_STOP#  
AGP_STOP#  
REF_STOP#  
35  
44  
45  
I
I
I
PCI STOP Input: This input will disable PCI0:8 and PCI9_E when it is active.  
AGP STOP Input: This input will disable AGP0:2 when it is active.  
REF STOP Input: This input will disable REF0:2, 24_48MHz and 48 MHz  
outputs when it is active.  
Rev 1.0,November 27, 2006  
Page 2 of 19  
1234567...19

下载PDF

与CYW312OXC相关器件

型号 品牌 描述 获取价格 数据表
CYW312OXCT SPECTRALINEAR FTG for VIA⑩ K7 Series Chipset with Programma

获取价格
CYW312OXCT CYPRESS FTG for VIA⑩ K7 Series Chipset with Programma

获取价格
CYW320OXC-3 SPECTRALINEAR 200 MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs

获取价格
CYW320OXC-3 CYPRESS 200-MHz Spread Spectrum Clock Synthesizer/Driver

获取价格
CYW320OXC-3T SPECTRALINEAR 200 MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs

获取价格
CYW320OXC-3T CYPRESS 200-MHz Spread Spectrum Clock Synthesizer/Driver

获取价格

与CYW312OXC相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证