Datasheet > 电信电路 > 网络接口> CYV15G0201DXB-BBI

CYV15G0201DXB-BBI

更新时间： 2024-02-04 02:43:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		网络接口电信集成电路电信电路信息通信管理以太网：16GBASE-T
页数	文件大小	规格书
46页	576K
描述
Dual-channel HOTLink II Transceiver

阅读下载

中文翻译

获取价格

技术参数
数据手册
替代型号

如果您发现信息不准确，欢迎纠错

CYV15G0201DXB-BBI 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	LBGA, BGA196,14X14,40
针数：	196	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.81
数据速率：	1500000 Mbps	JESD-30 代码：	S-PBGA-B196
JESD-609代码：	e1	长度：	15 mm
湿度敏感等级：	5	功能数量：	1
端子数量：	196	收发器数量：	2
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA196,14X14,40	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE	峰值回流温度（摄氏度）：	260
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1.5 mm	子类别：	Network Interfaces
最大压摆率：	0.71 mA	标称供电电压：	3.3 V
表面贴装：	YES	技术：	BICMOS
电信集成电路类型：	ETHERNET TRANSCEIVER	温度等级：	INDUSTRIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	20	宽度：	15 mm
Base Number Matches：	1

CYV15G0201DXB-BBI 数据手册

浏览型号CYV15G0201DXB-BBI的Datasheet PDF文件第7页

浏览型号CYV15G0201DXB-BBI的Datasheet PDF文件第8页

浏览型号CYV15G0201DXB-BBI的Datasheet PDF文件第9页

浏览型号CYV15G0201DXB-BBI的Datasheet PDF文件第11页

浏览型号CYV15G0201DXB-BBI的Datasheet PDF文件第12页

浏览型号CYV15G0201DXB-BBI的Datasheet PDF文件第13页

CYP15G0201DXB

CYV15G0201DXB

Pin Descriptions CYP(V)15G0201DXB Dual HOTLink II Transceiver (continued)

Pin Name I/OCharacteristics Signal Description

Differential LVPECL Reference Clock. This clock input is used as the timing reference for the transmit and

REFCLK

or single-ended

LVTTL input clock

receive PLLs. This input clock may also be selected to clock the transmit and receive parallel

interfaces. When driven by a single-ended LVCMOS or LVTTL clock source, connect the

clock source to either the true or complement REFCLK input, and leave the alternate

REFCLK input open (floating). When driven by an LVPECL clock source, the clock must be

a differential clock, using both inputs. When TXCKSEL = LOW, REFCLK is also used as the

clock for the parallel transmit data (input) interface. When RXCKSEL = LOW, the Elasticity

Buffer is enabled and REFCLK is used as the clock for the parallel receive data (output)

interface.

If the Elasticity Buffer is used, framing characters will be inserted or deleted to/from the data

stream to compensate for frequency differences between the reference clock and recovered

clock. When addition happens, a K28.5 will be appended immediately after a framing

character is detected in the Elasticity Buffer. When deletion happens, a framing character

will be removed from the datastream when detected in the Elasticity Buffer.

RXCLKC+

SPDSEL

3-state LVTTL

Output

Delayed REFCLK+ when RXCKSEL=LOW. Delayed form of REFCLK+, used for transfer

of recovered data to a host system. This output is only enabled when the receive parallel

interface is configured to present data relative to REFCLK (RXCKSEL = LOW).

3-Level Select^[5]

static control input

Serial Rate Select. This input specifies the operating bit-rate range of both transmit and

receive PLLs. LOW = 195–400 MBd, MID = 400–800 MBd, HIGH = 800–1500 MBd. When

SPDSEL is LOW, setting TXRATE = HIGH (Half-rate Reference Clock) is invalid.

LVTTL Input,

internal pull-up

Device Reset. Active LOW. Initializes all state machines and counters in the device.

TRSTZ

When sampled LOW by the rising edge of REFLCK, this input resets the internal state

machines and sets the Elasticity Buffer pointers to a nominal offset. When the reset is

removed (TRSTZ sampled HIGH by REFCLK↑), the status and data outputs will become

deterministic in less than 16 REFCLK cycles.

The BISTLE, OELE, and RXLE latches are reset by TRSTZ.

If the Elasticity Buffer or the Phase Align Buffer are used, TRSTZ should be applied after

power up to initialize the internal pointers into these memory arrays.

Analog I/O and Control

OUTA1

OUTB1

CML Differential

Output

Primary Differential Serial Data Outputs. These PECL-compatible CML outputs (+3.3V

referenced) are capable of driving terminated transmission lines or standard fiber-optic

transmitter modules.

OUTA2

OUTB2

CML Differential

Output

Secondary Differential Serial Data Outputs. These PECL-compatible CML outputs

(+3.3V referenced) are capable of driving terminated transmission lines or standard

fiber-optic transmitter modules.

INA1

INB1

LVPECL Differential Primary Differential Serial Data Inputs. These inputs accept the serial data stream for

Input

deserialization and decoding. The INx1 serial streams are passed to the receiver Clock

and Data Recovery (CDR) circuits to extract the data content when INSELx = HIGH.

INA2

INB2

LVPECL Differential Secondary Differential Serial Data Inputs. These inputs accept the serial data stream for

Input

deserialization and decoding. The INx2 serial streams are passed to the receiver Clock

and Data Recovery (CDR) circuits to extract the data content when INSELx = LOW.

INSELA

INSELB

LVTTL Input,

asynchronous

Receive Input Selector. Determines which external serial bit stream is passed to the

receiver Clock and Data Recovery circuit. When HIGH, the INx1 input is selected. When

LOW, the INx2 input is selected.

SDASEL

LPEN

3-Level Select ^[5]

Signal Detect Amplitude Level Select. Allows selection of one of three predefined

static configuration amplitude trip points for a valid signal indication, as listed in Table 11.

input

LVTTL Input,

asynchronous,

internal pull-down

All-Port Loop-Back-Enable. Active HIGH. When asserted (HIGH), the transmit serial data

from each channel is internally routed to the associated receiver Clock and Data Recovery

(CDR) circuit. All serial drivers are forced to differential logic “1”. All serial data inputs are

ignored.

Document #: 38-02058 Rev. *G

Page 10 of 46

1...7 8 91011 12 13...46

中文翻译

下载PDF

CYV15G0201DXB-BBI 替代型号

型号	品牌	替代类型	描述	数据表
CYV15G0201DXB-BBI	CYPRESS	当前型号	Dual-channel HOTLink II Transceiver
CYV15G0201DXB-BBXI	CYPRESS	功能相似	Dual-channel HOTLink II⑩ Transceiver
CYV15G0201DXB-BBXC	CYPRESS	功能相似	Dual-channel HOTLink II⑩ Transceiver
CYV15G0201DXB-BBC	CYPRESS	功能相似	Dual-channel HOTLink II Transceiver

与CYV15G0201DXB-BBI相关器件

型号	品牌	描述	获取价格	数据表
CYV15G0201DXB-BBXC	CYPRESS	Dual-channel HOTLink II⑩ Transceiver	获取价格
CYV15G0201DXB-BBXI	CYPRESS	Dual-channel HOTLink II⑩ Transceiver	获取价格
CYV15G0203TB	CYPRESS	Independent Clock Dual HOTLink II Serializer	获取价格
CYV15G0203TB_07	CYPRESS	Independent Clock Dual HOTLink II⑩ Serializer	获取价格
CYV15G0203TB_09	CYPRESS	Independent Clock Dual HOTLink II Serializer	获取价格
CYV15G0203TB-BGC	CYPRESS	Independent Clock Dual HOTLink II Serializer	获取价格
CYV15G0203TB-BGXC	CYPRESS	Independent Clock Dual HOTLink II⑩ Serializer	获取价格
CYV15G0204RB	CYPRESS	Independent Clock Dual HOTLink II⑩ Reclocking	获取价格
CYV15G0204RB_09	CYPRESS	Independent Clock Dual HOTLink II Reclocking Deserializer	获取价格
CYV15G0204RB-BGC	CYPRESS	Independent Clock Dual HOTLink II⑩ Reclocking	获取价格

与CYV15G0201DXB-BBI相关文章

晶闸管阳极与阴极之间加电压时控制极的电流流动分析
2024-06-05

2
探究MOS管沟道夹断后载流子传输机制及其电路设计影响
2024-06-05

4
光敏电阻的工作原理、作用及检测方法
2024-06-05

4
ENC28J60以太网控制器全面解析：特性、应用、引脚说明
2024-06-05

2

产品中心

服务支持

精选活动

关于我们

帮助中心

CYV15G0201DXB-BBI

CYV15G0201DXB-BBI 技术参数

CYV15G0201DXB-BBI 数据手册

CYV15G0201DXB-BBI 替代型号

与CYV15G0201DXB-BBI相关器件

与CYV15G0201DXB-BBI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CYV15G0201DXB-BBI

CYV15G0201DXB-BBI 技术参数

CYV15G0201DXB-BBI 数据手册

CYV15G0201DXB-BBI 替代型号

与CYV15G0201DXB-BBI相关器件

与CYV15G0201DXB-BBI相关文章

您还可以找

您在本页遇到什么问题？