Datasheet > CYUSB302X

CYUSB302X

更新时间： 2024-11-19 01:22:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
34页	779K
描述
SD3â¢ USB and Mass Storage Peripheral Controller

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中文翻译

获取价格

数据手册

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CYUSB302X 数据手册

CYUSB302x

SD3™ USB and Mass Storage

Peripheral Controller

SD3™ USB and Mass Storage Peripheral Controller

■ Independent power domains for core and I/O

Features

■ 10 × 10 mm, 0.8-mm pitch ball grid array (BGA) package

■ Latest-generation storage support

❐ SD3.0/SDXC – UHS1 SDR50 / DDR50 Master

❐ eMMC 4.4 Master

■ 5.099 mm × 4.695 mm × 0.55 mm, with 0.4 mm pitch small

footprint wafer-level chip scale package (WLCSP)

❐ SDIO 3.0 Master

Applications

■ USB integration

■ USB thumb drives

■ Card readers

❐ CertifiedUSB3.0andUSB2.0 peripheral: SuperSpeed (SS),

Hi-Speed (HS), and Full-Speed (FS) only)

❐ Thirty-two physical endpoints

❐ Integrated transceiver

❐ Accessory charger adaptor (ACA) support

■ Laptop with SD slots

■ SD slot in TV/STB

■ WIFI Dongles

■ Ultra low-power in core power-down mode

❐ Less than 60 µA with VBATT on and 20 µA with VBATT off

■ USB SDIO Bridge

■ Raid on-Chip Controller

■ I²C master controller at 1 MHz

■ Selectable input clock frequencies

❐ 19.2, 26, 38.4, and 52 MHz

❐ 19.2-MHz crystal input support

Logic Block Diagram

JTAG

Embedded

SRAm

(512 kB/

256 KB)

ARM926EJ-S

SSRX-

SSRX+

Peripheral

SSTX-

SSTX+

D+

USB

EPs

GPIOs

HS/FS

Peripheral

FSLC[0]

FSLC[1]

D-

FSLC[2]

UART

CLKIN

SDIO/SD/MMC Controller

CLKIN_32

XTALIN

SPI

XTALOUT

I²S

I2C

S0-PORT

S1-PORT

Errata: For information on silicon errata, see “Errata” on page 30. Details include trigger conditions, devices affected, and proposed workaround.

Cypress Semiconductor Corporation

Document Number: 001-55190 Rev. *L

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 15, 2017

12 3 4 5 6 7...34

中文翻译

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